Ejemplo n.º 1
0
void dsim_reg_set_porch(u32 id, struct decon_lcd *lcd)
{
	u32 val, mask, width;

	if (lcd->mode == DECON_VIDEO_MODE) {
		val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
			DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
			DSIM_MVPORCH_VBP(lcd->vbp);
		mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
			DSIM_MVPORCH_STABLE_VFP_MASK;
		dsim_write_mask(id, DSIM_MVPORCH, val, mask);

		val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
		dsim_write(id, DSIM_MHPORCH, val);

		val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
		mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
		dsim_write_mask(id, DSIM_MSYNC, val, mask);
	}

	if (lcd->mic_enabled)
		width = (lcd->xres/3) + (lcd->xres % 4);
	else
		width = lcd->xres;

	/* TODO: will be added SHADOW_EN in EVT1 */
	val = DSIM_MDRESOL_VRESOL(lcd->yres) | DSIM_MDRESOL_HRESOL(width);
	mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(id, DSIM_MDRESOL, val, mask);
}
void dsim_reg_set_porch(struct decon_lcd *lcd)
{
	u32 val, mask, width, height;

	if (lcd->mode == VIDEO_MODE) {
		val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
			DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
			DSIM_MVPORCH_VBP(lcd->vbp);
		mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
			DSIM_MVPORCH_STABLE_VFP_MASK;
		dsim_write_mask(DSIM_MVPORCH, val, mask);

		val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
		dsim_write(DSIM_MHPORCH, val);

		val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
		mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
		dsim_write_mask(DSIM_MSYNC, val, mask);
	}

	width = GET_W(lcd->hsync_2h_cycle, lcd->xres);
	height = GET_H(lcd->hsync_2h_cycle, lcd->yres);

	val = DSIM_MDRESOL_VRESOL(height) | DSIM_MDRESOL_HRESOL(width);
	mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(DSIM_MDRESOL, val, mask);
}
Ejemplo n.º 3
0
void dsim_reg_set_standby(u32 id, struct decon_lcd *lcd, u32 en)
{
	u32 val, mask;
	u32 width;

	if (lcd->mic_enabled)
		width = (lcd->xres/3) + (lcd->xres % 4);
	else
		width = lcd->xres;

	if (en) {
		val = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL(lcd->yres) |
			DSIM_MDRESOL_HRESOL(width);
		mask = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL_MASK |
			DSIM_MDRESOL_HRESOL_MASK;
	} else {
		val = DSIM_MDRESOL_VRESOL(lcd->yres) | DSIM_MDRESOL_HRESOL(width);
		mask = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL_MASK |
			DSIM_MDRESOL_HRESOL_MASK;
	}

	dsim_write_mask(id, DSIM_MDRESOL, val, mask);
}
Ejemplo n.º 4
0
/*
 * dsim main display configuration for window partial update
 *	- w : width for partial update
 *	- h : height for partial update
 *	- mic_on : MIC_ENABLE (1) / MIC_DISABLE (0)
 */
void dsim_reg_set_win_update_conf(int w, int h, bool mic_on)
{
	u32 val;
	u32 mask;

	if (mic_on)
		w = ((w >> 2) << 1) + (w & 0x3);
	/* Before setting config. disable standby */
	mask = DSIM_MDRESOL_STAND_BY;
	val = 0;
	dsim_write_mask(DSIM_MDRESOL, val, mask);

	val = DSIM_MDRESOL_VRESOL(h) | DSIM_MDRESOL_HRESOL(w) |
		DSIM_MDRESOL_STAND_BY;
	mask = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL_MASK |
		DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(DSIM_MDRESOL, val, mask);
}
/*
 * dsim main display configuration for window partial update
 *	- w : width for partial update
 *	- h : height for partial update
 *	- mic_on : MIC_ENABLE (1) / MIC_DISABLE (0)
 */
void dsim_reg_set_win_update_conf(int w, int h, struct decon_lcd *lcd)
{
	u32 val;
	u32 mask;

	w = GET_W(lcd->hsync_2h_cycle, w);
	h = GET_H(lcd->hsync_2h_cycle, h);

	/* Before setting config. disable standby */
	mask = DSIM_MDRESOL_STAND_BY;
	val = 0;
	dsim_write_mask(DSIM_MDRESOL, val, mask);

	val = DSIM_MDRESOL_VRESOL(h) | DSIM_MDRESOL_HRESOL(w) |
		DSIM_MDRESOL_STAND_BY;
	mask = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL_MASK |
		DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(DSIM_MDRESOL, val, mask);
}
Ejemplo n.º 6
0
		val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
		dsim_write(id, DSIM_MHPORCH, val);

		val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
		mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
		dsim_write_mask(id, DSIM_MSYNC, val, mask);
	}

	if (lcd->mic_enabled)
		width = (lcd->xres >> 1) + (lcd->xres % 4);
	else
		width = lcd->xres;

	/* TODO: will be added SHADOW_EN in EVT1 */
	val = DSIM_MDRESOL_VRESOL(lcd->yres) | DSIM_MDRESOL_HRESOL(width);
	mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(id, DSIM_MDRESOL, val, mask);
}

void dsim_reg_set_config(u32 id, u32 mode, u32 data_lane_cnt)
{
	u32 val = 0;
	u32 mask;

	if (mode == DECON_VIDEO_MODE) {
		val = DSIM_CONFIG_VIDEO_MODE;
	} else if (mode == DECON_MIPI_COMMAND_MODE) {
		val &= ~(DSIM_CONFIG_CLKLANE_STOP_START);   /* In Command mode, Clklane_Stop/Start must be disabled */
	} else {
		dsim_err("This DDI is not MIPI interface.\n");