__s32 BSP_disp_tv_open(__u32 sel)
{
if(!(gdisp.screen[sel].status & TV_ON))
{
__disp_tv_mode_t tv_mod;
tv_mod = gdisp.screen[sel].tv_mode;
image_clk_on(sel);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod);
tve_clk_on();
lcdc_clk_on(sel);
TCON1_set_tv_mode(sel,tv_mod);
TVE_set_tv_mode(sel, tv_mod);
Disp_TVEC_DacCfg(sel, tv_mod);
TCON1_open(sel);
Disp_TVEC_Open(sel);
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod);
gdisp.screen[sel].status |= TV_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV;
}
return DIS_SUCCESS;
}
__s32 BSP_disp_vga_open(__u32 sel)
{
if (!(gdisp.screen[sel].status & VGA_ON)) {
__disp_vga_mode_t vga_mode;
__u32 i = 0;
vga_mode = gdisp.screen[sel].vga_mode;
lcdc_clk_on(sel);
image_clk_on(sel);
/*
* set image normal channel start bit , because every
* de_clk_off( ) will reset this bit
*/
Image_open(sel);
tve_clk_on(sel);
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_VGA, vga_mode);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_VGA, 1);
#ifdef CONFIG_ARCH_SUN4I
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA);
#else
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA,
gdisp.screen[sel].
iep_status & DRC_USED);
#endif
DE_BE_set_display_size(sel, vga_mode_to_width(vga_mode),
vga_mode_to_height(vga_mode));
DE_BE_Output_Select(sel, sel);
TCON1_set_vga_mode(sel, vga_mode);
TVE_set_vga_mode(sel);
Disp_TVEC_Open(sel);
TCON1_open(sel);
for (i = 0; i < 4; i++) {
if (gdisp.screen[sel].dac_source[i] ==
DISP_TV_DAC_SRC_COMPOSITE) {
TVE_dac_set_source(1 - sel, i,
DISP_TV_DAC_SRC_COMPOSITE);
TVE_dac_sel(1 - sel, i, i);
}
}
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode);
gdisp.screen[sel].b_out_interlace = 0;
gdisp.screen[sel].status |= VGA_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_VGA;
Display_set_fb_timing(sel);
}
return DIS_SUCCESS;
}
__s32 bsp_disp_vga_open(__u32 screen_id)
{
if(!(gdisp.screen[screen_id].status & VGA_ON))
{
__disp_vga_mode_t vga_mode;
__u32 i = 0;
vga_mode = gdisp.screen[screen_id].vga_mode;
lcdc_clk_on(screen_id, 1, 0);
lcdc_clk_on(screen_id, 1, 1);
tcon_init(screen_id);
image_clk_on(screen_id, 1);
Image_open(screen_id);//set image normal channel start bit , because every de_clk_off( )will reset this bit
tve_clk_on(screen_id);
disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_VGA, vga_mode);
gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_VGA;
bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id));
DE_BE_set_display_size(screen_id, vga_mode_to_width(vga_mode), vga_mode_to_height(vga_mode));
DE_BE_Output_Select(screen_id, screen_id);
tcon1_set_vga_mode(screen_id,vga_mode);
TVE_set_vga_mode(screen_id);
Disp_TVEC_Open(screen_id);
tcon1_open(screen_id);
for(i=0; i<4; i++) {
if(gdisp.screen[screen_id].dac_source[i] == DISP_TV_DAC_SRC_COMPOSITE) {
TVE_dac_set_source(1-screen_id, i, DISP_TV_DAC_SRC_COMPOSITE);
TVE_dac_sel(1-screen_id, i, i);
}
}
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode);
gdisp.screen[screen_id].b_out_interlace = 0;
gdisp.screen[screen_id].status |= VGA_ON;
gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_VGA;
#ifdef __LINUX_OSAL__
Display_set_fb_timming(screen_id);
#endif
}
return DIS_SUCCESS;
}
__s32 bsp_disp_tv_open(__u32 screen_id)
{
if(!(gdisp.screen[screen_id].status & TV_ON))
{
__disp_tv_mode_t tv_mod;
tv_mod = gdisp.screen[screen_id].tv_mode;
image_clk_on(screen_id, 1);
Image_open(screen_id);//set image normal channel start bit , because every de_clk_off( )will reset this bit
disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_TV, tv_mod);
tve_clk_on(screen_id);
lcdc_clk_on(screen_id, 1, 0);
lcdc_clk_on(screen_id, 1, 1);
tcon_init(screen_id);
gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_TV;
bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id));
DE_BE_set_display_size(screen_id, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod));
DE_BE_Output_Select(screen_id, screen_id);
#if (defined CONFIG_ARCH_SUN5I)
__u32 scaler_index = 0;
DE_BE_Set_Outitl_enable(screen_id , disp_get_screen_scan_mode(tv_mod));
for(scaler_index=0; scaler_index<2; scaler_index++)
{
if((gdisp.scaler[scaler_index].status & SCALER_USED) && (gdisp.scaler[scaler_index].screen_index == screen_id))
{
if(disp_get_screen_scan_mode(tv_mod) == 1)//interlace output
{
Scaler_Set_Outitl(scaler_index, TRUE);
}
else
{
Scaler_Set_Outitl(scaler_index, FALSE);
}
}
}
#endif
tcon1_set_tv_mode(screen_id,tv_mod);
TVE_set_tv_mode(screen_id, tv_mod);
Disp_TVEC_DacCfg(screen_id, tv_mod);
tcon1_open(screen_id);
Disp_TVEC_Open(screen_id);
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod);
#ifdef __LINUX_OSAL__
{
disp_gpio_set_t gpio_info[1];
__hdle gpio_pa_shutdown;
__s32 ret;
memset(gpio_info, 0, sizeof(disp_gpio_set_t));
ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(disp_gpio_set_t)/sizeof(int));
if(ret == 0) {
gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1);
if(!gpio_pa_shutdown) {
DE_WRN("audio codec_wakeup request gpio fail!\n");
} else {
OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl");
}
}
}
#endif
gdisp.screen[screen_id].b_out_interlace = disp_get_screen_scan_mode(tv_mod);
gdisp.screen[screen_id].status |= TV_ON;
gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_TV;
#if (defined CONFIG_ARCH_SUN7I)
Disp_set_out_interlace(screen_id);
#endif
#ifdef __LINUX_OSAL__
Display_set_fb_timming(screen_id);
#endif
}
return DIS_SUCCESS;
}
__s32 BSP_disp_tv_open(__u32 sel)
{
if (!(gdisp.screen[sel].status & TV_ON)) {
__disp_tv_mode_t tv_mod;
tv_mod = gdisp.screen[sel].tv_mode;
image_clk_on(sel);
/*
* set image normal channel start bit , because every
* de_clk_off( )will reset this bit
*/
Image_open(sel);
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_TV, tv_mod);
tve_clk_on(sel);
lcdc_clk_on(sel);
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_TV,
gdisp.screen[sel].
iep_status & DRC_USED);
DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod),
tv_mode_to_height(tv_mod));
DE_BE_Output_Select(sel, sel);
if (sunxi_is_sun5i()) {
int scaler_index;
DE_BE_Set_Outitl_enable(sel,
Disp_get_screen_scan_mode(tv_mod));
for (scaler_index = 0; scaler_index < 2; scaler_index++)
if ((gdisp.scaler[scaler_index].
status & SCALER_USED)
&& (gdisp.scaler[scaler_index].
screen_index == sel)) {
/* interlace output */
if (Disp_get_screen_scan_mode(tv_mod) ==
1)
Scaler_Set_Outitl(scaler_index,
TRUE);
else
Scaler_Set_Outitl(scaler_index,
FALSE);
}
}
TCON1_set_tv_mode(sel, tv_mod);
TVE_set_tv_mode(sel, tv_mod);
Disp_TVEC_DacCfg(sel, tv_mod);
TCON1_open(sel);
Disp_TVEC_Open(sel);
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod);
Disp_de_flicker_enable(sel, TRUE);
{
user_gpio_set_t gpio_info[1];
__hdle gpio_pa_shutdown;
__s32 ret;
memset(gpio_info, 0, sizeof(user_gpio_set_t));
ret =
script_parser_fetch("audio_para", "audio_pa_ctrl",
(int *)gpio_info,
sizeof(user_gpio_set_t) /
sizeof(int));
if (ret < 0) {
DE_WRN("fetch script data "
"audio_para.audio_pa_ctrl fail\n");
} else {
gpio_pa_shutdown =
OSAL_GPIO_Request(gpio_info, 1);
if (!gpio_pa_shutdown) {
DE_WRN("audio codec_wakeup request "
"gpio fail!\n");
} else {
OSAL_GPIO_DevWRITE_ONEPIN_DATA
(gpio_pa_shutdown, 0,
"audio_pa_ctrl");
}
}
}
gdisp.screen[sel].b_out_interlace =
Disp_get_screen_scan_mode(tv_mod);
gdisp.screen[sel].status |= TV_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV;
Disp_set_out_interlace(sel);
Display_set_fb_timing(sel);
}
return DIS_SUCCESS;
}
__s32 BSP_disp_tv_open(__u32 sel)
{
if(!(gdisp.screen[sel].status & TV_ON))
{
__disp_tv_mode_t tv_mod;
tv_mod = gdisp.screen[sel].tv_mode;
image_clk_on(sel);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod);
tve_clk_on(sel);
lcdc_clk_on(sel);
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_TV);
DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod));
DE_BE_Output_Select(sel, sel);
TCON1_set_tv_mode(sel,tv_mod);
TVE_set_tv_mode(sel, tv_mod);
Disp_TVEC_DacCfg(sel, tv_mod);
TCON1_open(sel);
Disp_TVEC_Open(sel);
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod);
#ifdef __LINUX_OSAL__
{
user_gpio_set_t gpio_info[1];
__hdle gpio_pa_shutdown;
__s32 ret;
memset(gpio_info, 0, sizeof(user_gpio_set_t));
ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(user_gpio_set_t)/sizeof(int));
if(ret < 0)
{
DE_WRN("fetch script data audio_para.audio_pa_ctrl fail\n");
}
else
{
gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1);
if(!gpio_pa_shutdown)
{
DE_WRN("audio codec_wakeup request gpio fail!\n");
}
else
{
OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl");
}
}
}
#endif
gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod);
gdisp.screen[sel].status |= TV_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV;
Disp_set_out_interlace(sel);
#ifdef __LINUX_OSAL__
Display_set_fb_timming(sel);
#endif
}
return DIS_SUCCESS;
}