void
EDMA30ComplIsr(intptr_t unused) {
//
const unsigned int baseAdd = SOC_EDMA30CC_0_REGS;
const unsigned int regionNum = 0;
volatile unsigned int pendingIrqs;
volatile unsigned int isIPR = 0;
// unsigned int Cnt = 0;
// indexl = 1;
while((isIPR = HWREG(baseAdd + EDMA3CC_S_IPR(regionNum))) != 0)
{
// while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0u))
// {
unsigned int indexl = 0u;
pendingIrqs = HWREG(baseAdd + EDMA3CC_S_IPR(regionNum));
while (pendingIrqs)
{
if((pendingIrqs & 1u) == TRUE)
{
/**
* If the user has not given any callback function
* while requesting the TCC, its TCC specific bit
* in the IPR register will NOT be cleared.
*/
/* here write to ICR to clear the corresponding IPR bits */
HWREG(baseAdd + EDMA3CC_S_ICR(regionNum)) = (1u << indexl);
//(*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
#if defined(DEBUG)
syslog(LOG_ERROR, "%s(): Transfer request of channel %d is completed.", __FUNCTION__, indexl);
#endif
edma_isrs[indexl](edma_isr_exinfs[indexl]);
}
++indexl;
pendingIrqs >>= 1u;
}
// Cnt++;
// }
}
HWREG(baseAdd + EDMA3CC_IEVAL) = (EDMA3CC_IEVAL_EVAL << EDMA3CC_IEVAL_EVAL_SHIFT);
}
/*#####################################################*/
static void Edma3CompletionIsr(void)
{
volatile unsigned int pendingIrqs;
volatile unsigned int isIPR = 0;
unsigned int indexl;
unsigned int Cnt = 0;
indexl = 1;
isIPR = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_IPR(REGION_NUMBER));
if(isIPR)
{
while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0u))
{
indexl = 0u;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_IPR(REGION_NUMBER));
while (pendingIrqs)
{
if((pendingIrqs & 1u) == TRUE)
{
/**
* If the user has not given any callback function
* while requesting the TCC, its TCC specific bit
* in the IPR register will NOT be cleared.
*/
/* here write to ICR to clear the corresponding IPR bits */
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_ICR(REGION_NUMBER)) = (1u << indexl);
if (cb_Fxn[indexl] != NULL)
{
(*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
}
}
++indexl;
pendingIrqs >>= 1u;
}
Cnt++;
}
}
}
