/*
** Function to initialize the looping of tone.
*/
static void ToneLoopInit(void)
{
EDMA3Init(EDMA_INST_BASE, 0);
EDMA3RequestChannel(EDMA_INST_BASE, EDMA3_CHANNEL_TYPE_DMA,
EDMA_CHANNEL_IN_USE, EDMA_CHANNEL_IN_USE, 0);
/*
** To maintain portability, between GCC and TMS470, we initialize the
** BCNT for dmaPar[1] here. Else if the initialization is done above,
** TMS470 throws up error: expression must have a constant value
*/
dmaPar[1].bCnt = PARAM2_BCNT;
/* Initialize the DMA parameters */
EDMA3SetPaRAM(EDMA_INST_BASE, EDMA_CHANNEL_IN_USE,
(struct EDMA3CCPaRAMEntry *)(&(dmaPar[0])));
EDMA3SetPaRAM(EDMA_INST_BASE, 70,
(struct EDMA3CCPaRAMEntry *)(&(dmaPar[1])));
EDMA3SetPaRAM(EDMA_INST_BASE, 71,
(struct EDMA3CCPaRAMEntry *)(&(dmaPar[2])));
/* Configure the McASP for I2S with two channels */
McASPI2STwoChanConfig();
}
/*
** Initializes the DMA parameters.
** The RX basic paRAM set(channel) is 0 and TX basic paRAM set (channel) is 1.
**
** The RX paRAM set 0 will be initialized to receive data in the rx buffer 0.
** The transfer completion interrupt will not be enabled for paRAM set 0;
** paRAM set 0 will be linked to linked paRAM set starting (PAR_RX_START) of RX.
** and further reception only happens via linked paRAM set.
** For example, if the PAR_RX_START value is 40, and the number of paRAMS is 2,
** reception paRAM set linking will be initialized as 0-->40-->41-->40
**
** The TX paRAM sets will be initialized to transmit from the loop buffer.
** The size of the loop buffer can be configured.
** The transfer completion interrupt will not be enabled for paRAM set 1;
** paRAM set 1 will be linked to linked paRAM set starting (PAR_TX_START) of TX.
** All other paRAM sets will be linked to itself.
** and further transmission only happens via linked paRAM set.
** For example, if the PAR_RX_START value is 42, and the number of paRAMS is 2,
** So transmission paRAM set linking will be initialized as 1-->42-->42, 43->43.
*/
static void I2SDMAParamInit(void)
{
EDMA3CCPaRAMEntry paramSet;
int idx;
/* Initialize the 0th paRAM set for receive */
memcpy(¶mSet, &rxDefaultPar, SIZE_PARAMSET - 2);
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, ¶mSet);
/* further paramsets, enable interrupt */
paramSet.opt |= RX_DMA_INT_ENABLE;
for(idx = 0 ; idx < NUM_PAR; idx++)
{
paramSet.destAddr = rxBufPtr[idx];
paramSet.linkAddr = (PAR_RX_START + ((idx + 1) % NUM_PAR))
* (SIZE_PARAMSET);
paramSet.bCnt = NUM_SAMPLES_PER_AUDIO_BUF;
/*
** for the first linked paRAM set, start receiving the second
** sample only since the first sample is already received in
** rx buffer 0 itself.
*/
if( 0 == idx)
{
paramSet.destAddr += BYTES_PER_SAMPLE;
paramSet.bCnt -= BYTES_PER_SAMPLE;
}
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, (PAR_RX_START + idx), ¶mSet);
}
/* Initialize the required variables for reception */
nxtBufToRcv = idx % NUM_BUF;
lastFullRxBuf = NUM_BUF - 1;
parOffRcvd = 0;
/* Initialize the 1st paRAM set for transmit */
memcpy(¶mSet, &txDefaultPar, SIZE_PARAMSET);
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX, ¶mSet);
/* rest of the params, enable loop job */
for(idx = 0 ; idx < NUM_PAR; idx++)
{
ParamTxLoopJobSet(PAR_TX_START + idx);
}
/* Initialize the variables for transmit */
parOffSent = 0;
lastSentTxBuf = NUM_BUF - 1;
}
/*
** Assigns loop job for a parameter set
*/
static void ParamTxLoopJobSet(unsigned short parId)
{
EDMA3CCPaRAMEntry paramSet;
memcpy(¶mSet, &txDefaultPar, SIZE_PARAMSET - 2);
/* link the paRAM to itself */
paramSet.linkAddr = parId * SIZE_PARAMSET;
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, parId, ¶mSet);
}
/* Assumed that MMC controller is using 32-bit or 4-byte transfers. */
static void MMCSDRxDmaConfig(void *ptr,
unsigned int blkSize,
unsigned int nblks)
{
EDMA3CCPaRAMEntry paramSet;
unsigned int bytes;
#if DEBUG_PRINT
// UARTprintf("%s(%p,%d,%d)\r\n", __FUNCTION__, ptr, blkSize, nblks);
syslog(LOG_ERROR, "%s(%p,%d,%d)", __FUNCTION__, ptr, blkSize, nblks);
#endif
/* The block size must not be greater than the FIFO level of controller */
/* or else DMA interrupts diappear. Don't know why. */
/* Assumed that the incoming block size is an integer size of the */
/* FIFO level size. Divides evenly. */
bytes = blkSize * nblks;
if(bytes>64)
{
blkSize = 64;
nblks = bytes/64;
#if DEBUG_PRINT
// UARTprintf("%s(%p,%d,%d)\r\n", __FUNCTION__, ptr, blkSize, nblks);
syslog(LOG_ERROR, "%s(%p,%d,%d)", __FUNCTION__, ptr, blkSize, nblks);
#endif
}
paramSet.aCnt = 0x4; /* Item width in bytes */
paramSet.bCnt = (unsigned short)blkSize/4;/* Num of items in block.*/
paramSet.cCnt = (unsigned short)nblks; /* Num of blocks.*/
paramSet.srcAddr = ctrlInfo.memBase + MMCSD_MMCDRR;
paramSet.srcBIdx = 0; /* Index B increment */
paramSet.srcCIdx = 0; /* Index C increment */
paramSet.destAddr = (unsigned int)ptr;
paramSet.destBIdx = 4; /* Index B increment */
paramSet.destCIdx = (unsigned short)blkSize; /* Index C increment */
paramSet.bCntReload = 0x0;
paramSet.linkAddr = 0xffff;
paramSet.opt = 0;
paramSet.opt |= ((MMCSD_RX_EDMA_CHAN << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
paramSet.opt |= (1 << 2); /* SYNCDIM = 1 -> ABSYNC and SAM=0 -> NO FIFO */
EDMA3SetPaRAM(EDMA_INST_BASE, MMCSD_RX_EDMA_CHAN, ¶mSet);
EDMA3EnableTransfer(EDMA_INST_BASE, MMCSD_RX_EDMA_CHAN, EDMA3_TRIG_MODE_EVENT);
}
/*
** Activates the DMA transfer for a parameter set from the given buffer.
*/
static void BufferRxDMAActivate(unsigned int rxBuf, unsigned short parId,
unsigned short parLink)
{
EDMA3CCPaRAMEntry paramSet;
/* Copy the default paramset */
memcpy(¶mSet, &rxDefaultPar, SIZE_PARAMSET - 2);
/* Enable completion interrupt */
paramSet.opt |= RX_DMA_INT_ENABLE;
paramSet.destAddr = rxBufPtr[rxBuf];
paramSet.bCnt = NUM_SAMPLES_PER_AUDIO_BUF;
paramSet.linkAddr = parLink * SIZE_PARAMSET ;
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, parId, ¶mSet);
}
/*
** Activates the DMA transfer for a parameterset from the given buffer.
*/
void BufferTxDMAActivate(unsigned int txBuf, unsigned short numSamples,
unsigned short parId, unsigned short linkPar)
{
EDMA3CCPaRAMEntry paramSet;
/* Copy the default paramset */
memcpy(¶mSet, &txDefaultPar, SIZE_PARAMSET - 2);
/* Enable completion interrupt */
paramSet.opt |= TX_DMA_INT_ENABLE;
paramSet.srcAddr = txBufPtr[txBuf];
paramSet.linkAddr = linkPar * SIZE_PARAMSET;
paramSet.bCnt = numSamples;
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, parId, ¶mSet);
}
static void TxDummyPaRAMConfEnable(void)
{
EDMA3CCPaRAMEntry dummyPaRAMSet;
dummyPaRAMSet.aCnt = 1;
dummyPaRAMSet.bCnt = 0;
dummyPaRAMSet.cCnt = 0;
dummyPaRAMSet.srcAddr = 0;
dummyPaRAMSet.destAddr = 0;
dummyPaRAMSet.srcBIdx = 0;
dummyPaRAMSet.destBIdx = 0;
dummyPaRAMSet.srcCIdx = 0;
dummyPaRAMSet.destCIdx = 0;
dummyPaRAMSet.linkAddr = 0xFFFF;
dummyPaRAMSet.bCntReload = 0;
dummyPaRAMSet.opt = 0;
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, DUMMY_CH_NUM, &dummyPaRAMSet);
}
/*
** This function configures and sets the EDMA PaRAM set values for
** transferring data to UART TX FIFO.
*/
static void UARTTxEDMAPaRAMSetConfig(unsigned char *txBuffer,
unsigned int length,
unsigned int tccNum,
unsigned short linkAddr,
unsigned int chNum)
{
EDMA3CCPaRAMEntry paramSet;
/* Fill the PaRAM Set with transfer specific information. */
paramSet.srcAddr = (unsigned int) txBuffer;
paramSet.destAddr = (unsigned int)UART_THR_RHR_REG;
paramSet.aCnt = (unsigned short)1;
paramSet.bCnt = (unsigned short)txBytesPerEvent;
paramSet.cCnt = (unsigned short)(length / txBytesPerEvent);
paramSet.srcBIdx = (short)1;
paramSet.srcCIdx = (short)txBytesPerEvent;
/* The destination indexes should not increment since it is a h/w register. */
paramSet.destBIdx = (short)0;
paramSet.destCIdx = (short)0;
paramSet.linkAddr = (unsigned short)linkAddr;
paramSet.bCntReload = (unsigned short)0;
/* OPT PaRAM entries. */
paramSet.opt = (unsigned int)0x0;
/* Source and Destination addressing modes are Incremental. */
/* AB Synchronized Transfer. */
paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);
/* Setting the Transfer Complete Code(TCC). */
paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
/* Enabling the Completion Interrupt. */
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
/* Now write the PaRAM Set */
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, ¶mSet);
}
void HSMMCSDTxDmaConfig(void *ptr, unsigned int blkSize, unsigned int blks)
{
EDMA3CCPaRAMEntry paramSet;
paramSet.srcAddr = (unsigned int)ptr;
paramSet.destAddr = ctrlInfo.memBase + MMCHS_DATA;
paramSet.srcBIdx = 4;
paramSet.srcCIdx = blkSize;
paramSet.destBIdx = 0;
paramSet.destCIdx = 0;
paramSet.aCnt = 0x4;
paramSet.bCnt = (unsigned short)blkSize/4;
paramSet.cCnt = (unsigned short)blks;
paramSet.bCntReload = 0x0;
paramSet.linkAddr = 0xffff;
paramSet.opt = 0;
/* Set OPT */
paramSet.opt |= ((MMCSD_TX_EDMA_CHAN << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
/* 1. Transmission complition interrupt enable */
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
/* 2. Read FIFO : DST Constant addr mode */
paramSet.opt |= (1 << 1);
/* 3. DST FIFO width is 32 bit */
paramSet.opt |= (2 << 8);
/* 4. AB-Sync mode */
paramSet.opt |= (1 << 2);
/* configure PaRAM Set */
EDMA3SetPaRAM(EDMA_INST_BASE, MMCSD_TX_EDMA_CHAN, ¶mSet);
/* Enable the transfer */
EDMA3EnableTransfer(EDMA_INST_BASE, MMCSD_TX_EDMA_CHAN, EDMA3_TRIG_MODE_EVENT);
}
static void SpiRxEdmaParamSet(unsigned int tccNum, unsigned int chNum,
volatile char *buffer, unsigned int length,
unsigned int destBidxFlag)
{
EDMA3CCPaRAMEntry paramSet;
unsigned char *p = (unsigned char *)¶mSet;
unsigned int i = 0;
/* Clean-up the contents of structure variable. */
for (i = 0; i < sizeof(paramSet); i++)
{
p[i] = 0;
}
/* Fill the PaRAM Set with Receive specific information. */
/* srcAddr holds address of SPI Rx FIFO. */
paramSet.srcAddr = (unsigned int) (SOC_SPI_1_REGS + SPI_SPIBUF);
/* destAddr is address of memory location named buffer. */
paramSet.destAddr = (unsigned int) buffer;
/* aCnt holds the number of bytes in an array. */
paramSet.aCnt = (unsigned short) 1;
/* bCnt holds the number of such arrays to be transferred. */
paramSet.bCnt = (unsigned short) length;
/* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred. */
paramSet.cCnt = (unsigned short) 1;
/* The srcBidx should not be incremented since it is a h/w register. */
paramSet.srcBIdx = 0;
if(TRUE == destBidxFlag)
{
/* The destBidx should be incremented for every byte. */
paramSet.destBIdx = 1;
}
else
{
/* The destBidx should not be incremented. */
paramSet.destBIdx = 0;
}
/* A sync Transfer Mode. */
/* srCIdx and destCIdx set to zero since ASYNC Mode is used. */
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
/* Linking transfers in EDMA3 are not used. */
paramSet.linkAddr = (unsigned short)0xFFFF;
paramSet.bCntReload = 0;
paramSet.opt = 0x00000000;
/* Set TCC field in OPT with the tccNum. */
paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
/* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
/* Now write the PaRam Set to EDMA3.*/
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, ¶mSet);
/* EDMA3 Transfer is Enabled. */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);
}
/*
** This function is used to set the PaRAM entries of EDMA3 for the Transmit
** Channel of SPI1. The corresponding EDMA3 channel is also enabled for
** transmission.
*/
static void SpiTxEdmaParamSet(unsigned int tccNum, unsigned int chNum,
volatile char *buffer, unsigned int buffLength)
{
EDMA3CCPaRAMEntry paramSet;
unsigned char *p = (unsigned char *)¶mSet;
unsigned int i = 0;
/* Clean-up the contents of structure variable. */
for (i = 0; i < sizeof(paramSet); i++)
{
p[i] = 0;
}
/* Fill the PaRAM Set with transfer specific information. */
/* srcAddr holds address of memory location buffer. */
paramSet.srcAddr = (unsigned int) buffer;
/* destAddr holds address of SPIDAT1 register. */
paramSet.destAddr = (unsigned int) (SOC_SPI_1_REGS + SPI_SPIDAT1);
/* aCnt holds the number of bytes in an array. */
paramSet.aCnt = (unsigned short) 1;
/* bCnt holds the number of such arrays to be transferred. */
paramSet.bCnt = (unsigned short) buffLength;
/* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred. */
paramSet.cCnt = (unsigned short) 1;
/*
** The srcBidx should be incremented by aCnt number of bytes since the
** source used here is memory.
*/
paramSet.srcBIdx = (short) 1;
/* A sync Transfer Mode is set in OPT.*/
/* srCIdx and destCIdx set to zero since ASYNC Mode is used. */
paramSet.srcCIdx = (short) 0;
/* Linking transfers in EDMA3 are not used. */
paramSet.linkAddr = (unsigned short)0xFFFF;
paramSet.bCntReload = (unsigned short)0;
paramSet.opt = 0x00000000;
/* SAM field in OPT is set to zero since source is memory and memory
pointer needs to be incremented. DAM field in OPT is set to zero
since destination is not a FIFO. */
/* Set TCC field in OPT with the tccNum. */
paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
/* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
/* Now write the PaRam Set to EDMA3.*/
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, ¶mSet);
/* EDMA3 Transfer is Enabled. */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);
}
void EDMAAppEDMA3Test()
{
volatile unsigned int index = 0u;
volatile unsigned int count = 0u;
EDMA3CCPaRAMEntry paramSet;
unsigned char data = 0u;
volatile unsigned int retVal = 0u;
unsigned int isTestPassed = false;
unsigned int numEnabled = 0u;
unsigned int aCount = EDMAAPP_MAX_ACOUNT;
unsigned int bCount = EDMAAPP_MAX_BCOUNT;
unsigned int cCount = EDMAAPP_MAX_CCOUNT;
/* Initalize source and destination buffers */
for (count = 0u; count < (aCount * bCount * cCount); count++)
{
SrcBuff[count] = data++;
/*
** No need to initialize the destination buffer as it is
** being invalidated.
*/
}
/* Request DMA channel and TCC */
retVal = EDMA3RequestChannel(EDMAAPP_EDMACC_BASE_ADDRESS,
EDMAAPP_DMA_CH_TYPE, EDMAAPP_DMA_CH_NUM,
EDMAAPP_DMA_TCC_NUM, EDMAAPP_DMA_EVTQ);
/* Registering Callback Function */
EDMAAppCallbackFxn[EDMAAPP_DMA_TCC_NUM] = &EDMAAppCallback;
if(TRUE == retVal)
{
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (unsigned int)(SrcBuff);
paramSet.destAddr = (unsigned int)(DstBuff);
paramSet.aCnt = (unsigned short)aCount;
paramSet.bCnt = (unsigned short)bCount;
paramSet.cCnt = (unsigned short)cCount;
/* Setting up the SRC/DES Index */
paramSet.srcBIdx = (short)aCount;
paramSet.destBIdx = (short)aCount;
if(EDMA3_SYNC_A == EDMAAPP_DMA_SYNC_TYPE)
{
/* A Sync Transfer Mode */
paramSet.srcCIdx = (short)aCount;
paramSet.destCIdx = (short)aCount;
}
else
{
/* AB Sync Transfer Mode */
paramSet.srcCIdx = ((short)aCount * (short)bCount);
paramSet.destCIdx = ((short)aCount * (short)bCount);
}
/* Configure the paramset with NULL link */
paramSet.linkAddr = (unsigned short)0xFFFFu;
paramSet.bCntReload = (unsigned short)0u;
paramSet.opt = 0u;
/* Src & Dest are in INCR modes */
paramSet.opt &= ~(EDMA3CC_OPT_SAM | EDMA3CC_OPT_DAM);
/* Program the TCC */
paramSet.opt |= ((EDMAAPP_DMA_TCC_NUM << EDMA3CC_OPT_TCC_SHIFT)
& EDMA3CC_OPT_TCC);
/* Enable Intermediate & Final transfer completion interrupt */
paramSet.opt |= (1u << EDMA3CC_OPT_ITCINTEN_SHIFT);
paramSet.opt |= (1u << EDMA3CC_OPT_TCINTEN_SHIFT);
if(EDMA3_SYNC_A == EDMAAPP_DMA_SYNC_TYPE)
{
paramSet.opt &= ~EDMA3CC_OPT_SYNCDIM;
}
else
{
/* AB Sync Transfer Mode */
paramSet.opt |= (1u << EDMA3CC_OPT_SYNCDIM_SHIFT);
}
/* Now, write the PaRAM Set. */
EDMA3SetPaRAM(EDMAAPP_EDMACC_BASE_ADDRESS, EDMAAPP_DMA_CH_NUM,
¶mSet);
EDMA3GetPaRAM(EDMAAPP_EDMACC_BASE_ADDRESS, EDMAAPP_DMA_CH_NUM,
¶mSet);
}
/*
** Since the transfer is going to happen in Manual mode of EDMA3
** operation, we have to 'Enable the Transfer' multiple times.
** Number of times depends upon the Mode (A/AB Sync)
** and the different counts.
*/
if(TRUE == retVal)
{
/* Need to activate next param */
if(EDMA3_SYNC_A == EDMAAPP_DMA_SYNC_TYPE)
{
numEnabled = bCount * cCount;
}
else
{
/* AB Sync Transfer Mode */
numEnabled = cCount;
}
for(index = 0u; index < numEnabled; index++)
{
IrqRaised = EDMAAPP_IRQ_STATUS_XFER_INPROG;
/*
** Now enable the transfer as many times as calculated above.
*/
retVal = EDMA3EnableTransfer(EDMAAPP_EDMACC_BASE_ADDRESS,
EDMAAPP_DMA_CH_NUM,
EDMAAPP_DMA_TRIG_MODE);
/* Wait for the Completion ISR. */
while(EDMAAPP_IRQ_STATUS_XFER_INPROG == IrqRaised)
{
/*
** Wait for the Completion ISR on Master Channel.
** You can insert your code here to do something
** meaningful.
*/
}
/* Check the status of the completed transfer */
if(IrqRaised < (int)EDMAAPP_IRQ_STATUS_XFER_INPROG)
{
/* Some error occured, break from the FOR loop. */
ConsoleUtilsPrintf("\r\nEDMA3Test: Event Miss Occured!!!\r\n");
/* Clear the error bits first */
EDMA3ClearErrorBits(EDMAAPP_EDMACC_BASE_ADDRESS,
EDMAAPP_DMA_CH_NUM, EDMAAPP_DMA_EVTQ);
break;
}
}
}
/* Match the Source and Destination Buffers. */
if(TRUE == retVal)
{
for(index = 0u; index < (aCount * bCount * cCount); index++)
{
if(SrcBuff[index] != DstBuff[index])
{
isTestPassed = false;
ConsoleUtilsPrintf("EDMA3Test: Data write-read matching FAILED.\r\n");
ConsoleUtilsPrintf("The mismatch happened at index : %d\r\n",
((int)index + 1u));
break;
}
}
if(index == (aCount * bCount * cCount))
{
isTestPassed = true;
ConsoleUtilsPrintf("EDMA3Test: Data write-read matching PASSED.\r\n");
}
/* Free the previously allocated channel. */
retVal = EDMA3FreeChannel(EDMAAPP_EDMACC_BASE_ADDRESS,
EDMAAPP_DMA_CH_TYPE, EDMAAPP_DMA_CH_NUM,
EDMAAPP_DMA_TRIG_MODE, EDMAAPP_DMA_TCC_NUM,
EDMAAPP_DMA_EVTQ);
/* Unregister Callback Function */
EDMAAppCallbackFxn[EDMAAPP_DMA_TCC_NUM] = NULL;
if(TRUE != retVal)
{
ConsoleUtilsPrintf("EDMA3Test: EDMA3_DRV_freeChannel() FAILED.\r\n");
}
}
if(true == isTestPassed)
{
ConsoleUtilsPrintf("EDMA3Test PASSED.\r\n");
}
else
{
ConsoleUtilsPrintf("EDMA3Test FAILED\r\n");
}
}
/*
** This function is used to set the PaRAM entries of EDMA3 for the Transmit
** Channel 0 of SPI0 instance. The corresponding EDMA3 channel is also enabled
** for transmission.
*/
static void McSpiTxEdmaParamSet(unsigned int tccNum, unsigned int chNum,
volatile unsigned char *buffer,
unsigned short buffLength)
{
EDMA3CCPaRAMEntry paramSet;
unsigned char *p = (unsigned char *)¶mSet;
unsigned int index = 0;
/* Clean-up the contents of structure variable. */
for(index = 0; index < sizeof(paramSet); index++)
{
p[index] = 0;
}
/* Fill the PaRAM Set with transfer specific information. */
/* srcAddr holds address of memory location buffer. */
paramSet.srcAddr = (unsigned int) buffer;
/* destAddr holds address of McSPI_TX register. */
paramSet.destAddr = (unsigned int) (MCSPI_TX0_REG);
/* aCnt holds the number of bytes in an array. */
paramSet.aCnt = 1;
/* bCnt holds the number of such arrays to be transferred. */
paramSet.bCnt = buffLength;
/* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred. */
paramSet.cCnt = 1;
/*
** The srcBidx should be incremented by aCnt number of bytes since the
** source used here is memory.
*/
paramSet.srcBIdx = 1;
paramSet.destBIdx = 0;
/* Async Transfer Mode is set in OPT.*/
/* srCIdx and destCIdx set to zero since ASYNC Mode is used. */
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
/* Linking transfers in EDMA3 are not used. */
paramSet.linkAddr = (EDMA3CC_OPT(DUMMY_CH_NUM));
paramSet.bCntReload = 0;
paramSet.opt = 0x00000000;
/* SAM and DAM fields both are set to 0 */
/* Set TCC field in OPT with the tccNum. */
paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
/* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
/* Now write the PaRam Set to EDMA3.*/
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, ¶mSet);
/* Dummy param set is enabled */
TxDummyPaRAMConfEnable();
/* EDMA3 Transfer is Enabled. */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);
}
