static WRITE16_HANDLER( othunder_TC0220IOC_w )
{
if (ACCESSING_LSB)
{
switch (offset)
{
case 0x03:
/* 0000000x SOL-1 (gun solenoid)
000000x0 SOL-2 (gun solenoid)
00000x00 OBPRI (sprite priority)
0000x000 (unused)
000x0000 eeprom reset (active low)
00x00000 eeprom clock
0x000000 eeprom in data
x0000000 eeprom out data */
set_led_status(0, data & 1);
set_led_status(1, data & 2);
if (data & 4)
popmessage("OBPRI SET!");
EEPROM_write_bit(data & 0x40);
EEPROM_set_clock_line((data & 0x20) ? ASSERT_LINE : CLEAR_LINE);
EEPROM_set_cs_line((data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
break;
default:
TC0220IOC_w(offset,data & 0xff);
}
}
}
static WRITE16_HANDLER( eeprom_w )
{
if( ACCESSING_LSB )
{
EEPROM_write_bit(data & 0x01);
EEPROM_set_cs_line((data & 0x02) ? CLEAR_LINE : ASSERT_LINE );
EEPROM_set_clock_line((data & 0x04) ? ASSERT_LINE : CLEAR_LINE );
}
}
static WRITE8_HANDLER( eeprom_w )
{
/* bit 7 is data */
/* bit 6 is clock (active high) */
/* bit 5 is cs (active low) */
EEPROM_write_bit(data & 0x80);
EEPROM_set_cs_line((data & 0x20) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x40) ? ASSERT_LINE : CLEAR_LINE);
}
static WRITE32_HANDLER( avengrs_eprom_w )
{
if (mem_mask==0xffff00ff) {
UINT8 ebyte=(data>>8)&0xff;
// if (ebyte&0x80) {
EEPROM_set_clock_line((ebyte & 0x2) ? ASSERT_LINE : CLEAR_LINE);
EEPROM_write_bit(ebyte & 0x1);
EEPROM_set_cs_line((ebyte & 0x4) ? CLEAR_LINE : ASSERT_LINE);
// }
}
static WRITE16_HANDLER( inufuku_eeprom_w )
{
// latch the bit
EEPROM_write_bit(data & 0x0800);
// reset line asserted: reset.
EEPROM_set_cs_line((data & 0x2000) ? CLEAR_LINE : ASSERT_LINE);
// clock line asserted: write latch or select next bit to read
EEPROM_set_clock_line((data & 0x1000) ? ASSERT_LINE : CLEAR_LINE);
}
static WRITE32_HANDLER( polygonet_eeprom_w )
{
if (ACCESSING_MSB32)
{
EEPROM_write_bit((data & 0x01000000) ? ASSERT_LINE : CLEAR_LINE);
EEPROM_set_cs_line((data & 0x02000000) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x04000000) ? ASSERT_LINE : CLEAR_LINE);
return;
}
logerror("unknown write %x (mask %x) to eeprom\n", data, mem_mask);
}
static WRITE8_HANDLER( control2_w )
{
/* bit 0 is data */
/* bit 1 is cs (active low) */
/* bit 2 is clock (active high) */
cur_control2 = data;
EEPROM_write_bit(cur_control2 & 0x01);
EEPROM_set_cs_line((cur_control2 & 0x02) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((cur_control2 & 0x04) ? ASSERT_LINE : CLEAR_LINE);
}
void simpsons_eeprom_w( int offset, int data )
{
if ( data == 0xff )
return;
EEPROM_write_bit(data & 0x80);
EEPROM_set_cs_line((data & 0x08) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x10) ? ASSERT_LINE : CLEAR_LINE);
simpsons_video_banking( data & 3 );
simpsons_firq_enabled = data & 0x04;
}
static WRITE32_HANDLER( superchs_input_w )
{
#if 0
{
char t[64];
static UINT32 mem[2];
COMBINE_DATA(&mem[offset]);
sprintf(t,"%08x %08x",mem[0],mem[1]);
//ui_popup(t);
}
#endif
switch (offset)
{
case 0x00:
{
if (ACCESSING_MSB32) /* $300000 is watchdog */
{
watchdog_reset_w(0,data >> 24);
}
if (ACCESSING_LSB32)
{
EEPROM_set_clock_line((data & 0x20) ? ASSERT_LINE : CLEAR_LINE);
EEPROM_write_bit(data & 0x40);
EEPROM_set_cs_line((data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
return;
}
return;
}
/* there are 'vibration' control bits somewhere! */
case 0x01:
{
if (ACCESSING_MSB32)
{
coin_lockout_w(0,~data & 0x01000000);
coin_lockout_w(1,~data & 0x02000000);
coin_counter_w(0, data & 0x04000000);
coin_counter_w(1, data & 0x08000000);
coin_word=(data >> 16) &0xffff;
}
}
}
}
static WRITE16_HANDLER( esd_eeprom_w )
{
if (ACCESSING_MSB)
{
// data line
EEPROM_write_bit((data & 0x0400) >> 6);
// clock line asserted.
EEPROM_set_clock_line((data & 0x0200) ? ASSERT_LINE : CLEAR_LINE );
// reset line asserted: reset.
EEPROM_set_cs_line((data & 0x0100) ? CLEAR_LINE : ASSERT_LINE );
}
// logerror("(0x%06x) Unk EEPROM write: %04x %04x\n", activecpu_get_pc(), data, mem_mask);
}
static WRITE8_HANDLER( control2_w )
{
/* bit 0 is data */
/* bit 1 is cs (active low) */
/* bit 2 is clock (active high) */
/* bit 3 is "MUT" on the schematics (audio mute?) */
/* bit 4 bankswitches the 4800-4fff region: 0 = registers, 1 = RAM ("CBNK" on schematics) */
/* bit 6 is "SHD0" (some kind of shadow control) */
/* bit 7 is "SHD1" (ditto) */
cur_control2 = data;
EEPROM_write_bit(cur_control2 & 0x01);
EEPROM_set_cs_line((cur_control2 & 0x02) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((cur_control2 & 0x04) ? ASSERT_LINE : CLEAR_LINE);
}
static WRITE16_HANDLER( control2_w )
{
if (ACCESSING_LSB)
{
cur_control2 = data;
/* bit 0 is data */
/* bit 1 is cs (active low) */
/* bit 2 is clock (active high) */
EEPROM_write_bit(data & 0x01);
EEPROM_set_cs_line((data & 0x02) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x04) ? ASSERT_LINE : CLEAR_LINE);
/* bit 5 is select tile bank */
K056832_set_tile_bank((data & 0x20) >> 5);
}
}
static WRITE16_HANDLER( kickgoal_eeprom_w )
{
if (ACCESSING_LSB)
{
switch (offset)
{
case 0:
EEPROM_set_cs_line((data & 0x0001) ? CLEAR_LINE : ASSERT_LINE);
break;
case 1:
EEPROM_set_clock_line((data & 0x0001) ? ASSERT_LINE : CLEAR_LINE);
break;
case 2:
EEPROM_write_bit(data & 0x0001);
break;
}
}
}
static WRITE16_HANDLER( control2_w )
{
if(ACCESSING_LSB) {
/* bit 0 is data */
/* bit 1 is cs (active low) */
/* bit 2 is clock (active high) */
/* bit 3 (unknown: coin) */
/* bit 5 is enable irq 6 */
/* bit 7 (unknown: enable irq 5?) */
EEPROM_write_bit(data & 0x01);
EEPROM_set_cs_line((data & 0x02) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x04) ? ASSERT_LINE : CLEAR_LINE);
cur_control2 = data;
/* bit 6 = enable sprite ROM reading */
K053246_set_OBJCHA_line((data & 0x0040) ? ASSERT_LINE : CLEAR_LINE);
}
}
static WRITE32_HANDLER( control_w )
{
// bit $80000000 = BSMT access/ROM read
// bit $20000000 = toggled every 64 IRQ4's
// bit $10000000 = ????
// bit $00800000 = EEPROM data
// bit $00400000 = EEPROM clock
// bit $00200000 = EEPROM enable (on 1)
COMBINE_DATA(&control_data);
/* handle EEPROM I/O */
if (!(mem_mask & 0x00ff0000))
{
EEPROM_write_bit(data & 0x00800000);
EEPROM_set_cs_line((data & 0x00200000) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x00400000) ? ASSERT_LINE : CLEAR_LINE);
}
/* log any unknown bits */
if (data & 0x4f1fffff)
logerror("%08X: control_w = %08X & %08X\n", activecpu_get_previouspc(), data, ~mem_mask);
}
static WRITE16_HANDLER( eeprom_w )
{
logerror("%06x: write %04x to 108000\n",activecpu_get_pc(),data);
if (ACCESSING_LSB)
{
/* bit 0 = coin counter */
coin_counter_w(0,data & 0x01);
/* bit 2 is data */
/* bit 3 is clock (active high) */
/* bit 4 is cs (active low) */
EEPROM_write_bit(data & 0x04);
EEPROM_set_cs_line((data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x08) ? ASSERT_LINE : CLEAR_LINE);
}
if (ACCESSING_MSB)
{
/* bit 8 = enable sprite ROM reading */
K053246_set_OBJCHA_line((data & 0x0100) ? ASSERT_LINE : CLEAR_LINE);
/* bit 9 = enable char ROM reading through the video RAM */
K052109_set_RMRD_line((data & 0x0200) ? ASSERT_LINE : CLEAR_LINE);
}
}
static WRITE16_HANDLER( eeprom_chip_select_w )
{
/* bit 0 is CS (active low) */
EEPROM_set_cs_line((data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
}
static WRITE8_HANDLER( eeprom_w )
{
EEPROM_write_bit(data & 0x04);
EEPROM_set_cs_line((data & 0x02) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x08) ? ASSERT_LINE : CLEAR_LINE);
}
static WRITE8_HANDLER( eeprom_cs_w )
{
EEPROM_set_cs_line(data ? CLEAR_LINE : ASSERT_LINE);
}
