VOID RTMP_EEPROM_WRITE16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
IN USHORT Data)
{
UINT32 x;
#ifdef RT2870
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif
Offset /= 2;
EWEN(pAd);
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!IS_RT3090(pAd))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode ,register number and data in that order
ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
ShiftOutBits(pAd, Data, 16); // 16-bit access
// read DO status
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
EEpromCleanup(pAd);
RTMPusecDelay(10000); //delay for twp(MAX)=10ms
EWDS(pAd);
EEpromCleanup(pAd);
#ifdef RT2870
// Antenna and EEPROM access are both using EESK pin,
// Therefor we should avoid accessing EESK at the same time
// Then restore antenna after EEPROM access
if ((pAd->NicConfig2.field.AntDiversity) || (pAd->RfIcType == RFIC_3020))
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif
}
int rtmp_ee_prom_write16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
IN USHORT Data)
{
UINT32 x;
#ifdef RT30xx
#endif // RT30xx //
Offset /= 2;
EWEN(pAd);
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode ,register number and data in that order
ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
ShiftOutBits(pAd, Data, 16); // 16-bit access
// read DO status
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
EEpromCleanup(pAd);
RTMPusecDelay(10000); //delay for twp(MAX)=10ms
EWDS(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#endif // RT30xx //
return NDIS_STATUS_SUCCESS;
}
//*****************************************************************************
//
// I/O based Read EEPROM Routines
//
//*****************************************************************************
//-----------------------------------------------------------------------------
// Procedure: ReadEEprom
//
// Description: This routine serially reads one word out of the EEPROM.
//
// Arguments:
// Reg - EEPROM word to read.
//
// Returns:
// Contents of EEPROM word (Reg).
//-----------------------------------------------------------------------------
static USHORT
ReadEEprom(
struct rtl8190_priv *priv,
UCHAR AddressSize,
USHORT Reg)
{
ULONG ioaddr = priv->pshare->ioaddr;
USHORT x;
USHORT data;
// select EEPROM, reset bits, set EECS
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI | EEDO | EESK | CR9346_EEM0);
x |= CR9346_EEM1 | EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
ShiftOutBits(priv, EEPROM_READ_OPCODE, 3);
ShiftOutBits(priv, Reg, AddressSize);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(priv);
EEpromCleanup(priv);
return data;
}
USHORT ReadEEprom(
IN PFDO_DATA FdoData,
IN PUCHAR CSRBaseIoAddress,
IN USHORT Reg,
IN USHORT AddressSize)
{
USHORT x;
USHORT data;
// select EEPROM, reset bits, set EECS
x = FdoData->ReadPort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG));
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
FdoData->WritePort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG), x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
ShiftOutBits(FdoData, EEPROM_READ_OPCODE, 3, CSRBaseIoAddress);
ShiftOutBits(FdoData, Reg, AddressSize, CSRBaseIoAddress);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(FdoData, CSRBaseIoAddress);
EEpromCleanup(FdoData, CSRBaseIoAddress);
return data;
}
static VOID
WriteEEprom(
struct rtl8190_priv *priv,
UCHAR AddressSize,
USHORT reg,
USHORT data)
{
ULONG ioaddr = priv->pshare->ioaddr;
UCHAR x;
// select EEPROM, mask off ASIC and reset bits, set EECS
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI | EEDO | EESK | CR9346_EEM0);
x |= CR9346_EEM1 | EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
ShiftOutBits(priv, EEPROM_EWEN_OPCODE, 5);
/////ShiftOutBits(CSRBaseIoAddress, reg, 4);
ShiftOutBits(priv, 0, 6);
StandBy(priv);
// Erase this particular word. Write the erase opcode and register
// number in that order. The opcode is 3bits in length; reg is 6 bits long.
ShiftOutBits(priv, EEPROM_ERASE_OPCODE, 3);
ShiftOutBits(priv, reg, AddressSize);
if (WaitEEPROMCmdDone(priv) == FALSE)
{
return;
}
StandBy(priv);
// write the new word to the EEPROM
// send the write opcode the EEPORM
ShiftOutBits(priv, EEPROM_WRITE_OPCODE, 3);
// select which word in the EEPROM that we are writing to.
ShiftOutBits(priv, reg, AddressSize);
// write the data to the selected EEPROM word.
ShiftOutBits(priv, data, 16);
if (WaitEEPROMCmdDone(priv) == FALSE)
{
// DbgPrint("D100: Failed EEPROM Write");
return;
}
StandBy(priv);
ShiftOutBits(priv, EEPROM_EWDS_OPCODE, 5);
ShiftOutBits(priv, reg, 4);
EEpromCleanup(priv);
return;
}
// IRQL = PASSIVE_LEVEL
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif // ANT_DIVERSITY_SUPPORT //
#endif // RT30xx //
Offset /= 2;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!IS_RT3090(pAd))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode and register number in that order
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
// Antenna and EEPROM access are both using EESK pin,
// Therefor we should avoid accessing EESK at the same time
// Then restore antenna after EEPROM access
if ((pAd->NicConfig2.field.AntDiversity)/* || (pAd->RfIcType == RFIC_3020)*/)
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif // ANT_DIVERSITY_SUPPORT //
#endif // RT30xx //
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif
#endif
Offset /= 2;
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)))
{
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#ifdef ANT_DIVERSITY_SUPPORT
if ((pAd->NicConfig2.field.AntDiversity))
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif
#endif
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
USHORT GetEEpromSize(
IN PFDO_DATA FdoData,
IN PUCHAR CSRBaseIoAddress)
{
USHORT x, data;
USHORT size = 1;
// select EEPROM, reset bits, set EECS
x = FdoData->ReadPort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG));
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
FdoData->WritePort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG), x);
// write the read opcode
ShiftOutBits(FdoData, EEPROM_READ_OPCODE, 3, CSRBaseIoAddress);
// experiment to discover the size of the eeprom. request register zero
// and wait for the eeprom to tell us it has accepted the entire address.
x = FdoData->ReadPort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG));
do
{
size *= 2; // each bit of address doubles eeprom size
x |= EEDO; // set bit to detect "dummy zero"
x &= ~EEDI; // address consists of all zeros
FdoData->WritePort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG), x);
KeStallExecutionProcessor(100);
RaiseClock(FdoData, &x, CSRBaseIoAddress);
LowerClock(FdoData, &x, CSRBaseIoAddress);
// check for "dummy zero"
x = FdoData->ReadPort((PUSHORT)(CSRBaseIoAddress + CSR_EEPROM_CONTROL_REG));
if (size > EEPROM_MAX_SIZE)
{
size = 0;
break;
}
}
while (x & EEDO);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(FdoData, CSRBaseIoAddress);
EEpromCleanup(FdoData, CSRBaseIoAddress);
return size;
}
// IRQL = PASSIVE_LEVEL
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef RT30xx
#endif // RT30xx //
Offset /= 2;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// patch can not access e-Fuse issue
if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)))
{
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
// output the read_opcode and register number in that order
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef RT30xx
#endif // RT30xx //
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
static inline VOID EWDS(
IN PRTMP_ADAPTER pAd)
{
UINT32 x;
// reset bits and set EECS
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
// kick a pulse
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
// output the read_opcode and six pulse in that order
ShiftOutBits(pAd, EEPROM_EWDS_OPCODE, 5);
ShiftOutBits(pAd, 0, 6);
EEpromCleanup(pAd);
}
static inline VOID EWDS(
IN PRTMP_ADAPTER pAd)
{
UINT32 x;
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
ShiftOutBits(pAd, EEPROM_EWDS_OPCODE, 5);
ShiftOutBits(pAd, 0, 6);
EEpromCleanup(pAd);
}
int rtmp_ee_prom_write16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
IN USHORT Data)
{
UINT32 x;
#ifdef ANT_DIVERSITY_SUPPORT
/* Old chips use single circuit to contorl EEPROM and AntDiversity, so need protect. */
/* AntDiversity of RT5390 is independence internal circuit, so doesn't need protect. */
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif /* ANT_DIVERSITY_SUPPORT */
Offset /= 2;
EWEN(pAd);
/* reset bits and set EECS*/
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
/* patch can not access e-Fuse issue*/
if (IS_RT2860(pAd)
)
{
/* kick a pulse*/
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
/* output the read_opcode ,register number and data in that order */
ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
ShiftOutBits(pAd, Data, 16); /* 16-bit access*/
/* read DO status*/
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
EEpromCleanup(pAd);
RTMPusecDelay(10000); /*delay for twp(MAX)=10ms*/
EWDS(pAd);
EEpromCleanup(pAd);
#ifdef ANT_DIVERSITY_SUPPORT
/* Antenna and EEPROM access are both using EESK pin,*/
/* Therefor we should avoid accessing EESK at the same time*/
/* Then restore antenna after EEPROM access*/
/* AntDiversity of RT5390 is independence internal circuit, so doesn't need protect. */
if ((pAd->NicConfig2.field.AntDiversity)
#ifdef RT3290
&& (!IS_RT3290(pAd))
#endif /* RT3290 */
)
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif /* ANT_DIVERSITY_SUPPORT */
return NDIS_STATUS_SUCCESS;
}
/* IRQL = PASSIVE_LEVEL*/
int rtmp_ee_prom_read16(
IN PRTMP_ADAPTER pAd,
IN USHORT Offset,
OUT USHORT *pValue)
{
UINT32 x;
USHORT data;
#ifdef ANT_DIVERSITY_SUPPORT
/*
Old chips use single circuit to contorl EEPROM and AntDiversity, so need protect.
AntDiversity of RT5390 is independence internal circuit, so doesn't need protect.
*/
if (pAd->NicConfig2.field.AntDiversity)
{
pAd->EepromAccess = TRUE;
}
#endif /* ANT_DIVERSITY_SUPPORT */
Offset /= 2;
/* reset bits and set EECS*/
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
/* patch can not access e-Fuse issue*/
if (IS_RT2860(pAd))
{
/* kick a pulse*/
RaiseClock(pAd, &x);
LowerClock(pAd, &x);
}
/* output the read_opcode and register number in that order */
ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
/* Now read the data (16 bits) in from the selected EEPROM word*/
data = ShiftInBits(pAd);
EEpromCleanup(pAd);
#ifdef ANT_DIVERSITY_SUPPORT
/* Antenna and EEPROM access are both using EESK pin,*/
/* Therefor we should avoid accessing EESK at the same time*/
/* Then restore antenna after EEPROM access*/
/*AntDiversity of RT5390 is independence internal circuit, so doesn't need protect.*/
if ((pAd->NicConfig2.field.AntDiversity)
#ifdef RT3290
&& (!IS_RT3290(pAd))
#endif /* RT3290 */
)
{
pAd->EepromAccess = FALSE;
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
}
#endif /* ANT_DIVERSITY_SUPPORT */
*pValue = data;
return NDIS_STATUS_SUCCESS;
}
