static void
imxehci_select_interface(struct imxehci_softc *sc, enum imx_usb_if interface)
{
uint32_t reg;
struct ehci_softc *hsc = &sc->sc_hsc;
reg = EOREAD4(hsc, EHCI_PORTSC(1));
reg &= ~(PORTSC_PTS | PORTSC_PTW);
switch (interface) {
case IMXUSBC_IF_UTMI_WIDE:
reg |= PORTSC_PTW_16;
case IMXUSBC_IF_UTMI:
reg |= PORTSC_PTS_UTMI;
break;
case IMXUSBC_IF_PHILIPS:
reg |= PORTSC_PTS_PHILIPS;
break;
case IMXUSBC_IF_ULPI:
reg |= PORTSC_PTS_ULPI;
break;
case IMXUSBC_IF_SERIAL:
reg |= PORTSC_PTS_SERIAL;
break;
}
EOWRITE4(hsc, EHCI_PORTSC(1), reg);
}
static void
zynqusb_init(struct ehci_softc *hsc)
{
struct zynqehci_softc *sc = device_private(hsc->sc_dev);
uint32_t reg;
reg = EOREAD4(hsc, EHCI_PORTSC(1));
reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC);
reg |= EHCI_PS_PP | EHCI_PS_PE;
EOWRITE4(hsc, EHCI_PORTSC(1), reg);
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC);
reg |= OTGSC_IDPU;
reg |= OTGSC_DPIE | OTGSC_IDIE;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC, reg);
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE);
reg &= ~USBMODE_CM;
reg |= USBMODE_CM_HOST;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE, reg);
}
static void
imxehci_init(struct ehci_softc *hsc)
{
struct imxehci_softc *sc = device_private(hsc->sc_dev);
uint32_t reg;
reg = EOREAD4(hsc, EHCI_PORTSC(1));
reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC);
reg |= EHCI_PS_PP | EHCI_PS_PE;
EOWRITE4(hsc, EHCI_PORTSC(1), reg);
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC);
reg |= OTGSC_IDPU;
/* disable IDIE not to conflict with SSP1_DETECT. */
//reg |= OTGSC_DPIE | OTGSC_IDIE;
reg |= OTGSC_DPIE;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC, reg);
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_USBMODE);
reg &= ~USBMODE_CM;
reg |= USBMODE_CM_HOST;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_USBMODE, reg);
}
/* Handler for EHCI controller on entry to S3/S4/S5 */
void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
{
u32 reg32;
u8 *bar0_base;
u16 pwr_state;
u16 pci_cmd;
/* Check if the controller is disabled or not present */
bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff)
return;
pci_cmd = pci_read_config32(dev, PCI_COMMAND);
switch (slp_typ) {
case SLP_TYP_S4:
case SLP_TYP_S5:
/* Check if controller is in D3 power state */
pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS);
if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
/* Put in D0 */
u32 new_state = pwr_state & ~PWR_CTL_SET_MASK;
new_state |= PWR_CTL_SET_D0;
pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
/* Make sure memory bar is set */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base);
/* Make sure memory space is enabled */
pci_write_config16(dev, PCI_COMMAND, pci_cmd |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
/*
* If Run/Stop (bit0) is clear in USB2.0_CMD:
* - Clear Async Schedule Enable (bit5) and
* - Clear Periodic Schedule Enable (bit4) and
* - Set Run/Stop (bit0)
*/
reg32 = read32(bar0_base + EHCI_USB_CMD);
if (reg32 & EHCI_USB_CMD_RUN) {
reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE);
reg32 |= EHCI_USB_CMD_RUN;
write32(bar0_base + EHCI_USB_CMD, reg32);
}
/* Check for Port Enabled in PORTSC(0) (RMH) */
reg32 = read32(bar0_base + EHCI_PORTSC(0));
if (reg32 & EHCI_PORTSC_ENABLED) {
/* Set suspend bit in PORTSC if not already set */
if (!(reg32 & EHCI_PORTSC_SUSPEND)) {
reg32 |= EHCI_PORTSC_SUSPEND;
write32(bar0_base + EHCI_PORTSC(0), reg32);
}
/* Delay 25ms !! */
udelay(25 * 1000);
/* Clear Run/Stop bit */
reg32 = read32(bar0_base + EHCI_USB_CMD);
reg32 &= EHCI_USB_CMD_RUN;
write32(bar0_base + EHCI_USB_CMD, reg32);
}
/* Restore state to D3 if that is what it was at the start */
if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
/* Restore pci command reg */
pci_write_config16(dev, PCI_COMMAND, pci_cmd);
/* Enable D3 */
pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state);
}
}
}
void
imxehci_attach(struct device *parent, struct device *self, void *aux)
{
struct imxehci_softc *sc = (struct imxehci_softc *)self;
struct armv7_attach_args *aa = aux;
usbd_status r;
char *devname = sc->sc.sc_bus.bdev.dv_xname;
sc->sc.iot = aa->aa_iot;
sc->sc.sc_bus.dmatag = aa->aa_dmat;
sc->sc.sc_size = aa->aa_dev->mem[0].size;
/* Map I/O space */
if (bus_space_map(sc->sc.iot, aa->aa_dev->mem[0].addr,
aa->aa_dev->mem[0].size, 0, &sc->sc.ioh)) {
printf(": cannot map mem space\n");
goto out;
}
if (bus_space_map(sc->sc.iot, aa->aa_dev->mem[1].addr,
aa->aa_dev->mem[1].size, 0, &sc->uh_ioh)) {
printf(": cannot map mem space\n");
goto mem0;
}
if (bus_space_map(sc->sc.iot, aa->aa_dev->mem[2].addr,
aa->aa_dev->mem[2].size, 0, &sc->ph_ioh)) {
printf(": cannot map mem space\n");
goto mem1;
}
if (bus_space_map(sc->sc.iot, aa->aa_dev->mem[3].addr,
aa->aa_dev->mem[3].size, 0, &sc->nc_ioh)) {
printf(": cannot map mem space\n");
goto mem2;
}
printf("\n");
imxccm_enable_usboh3();
delay(1000);
if (aa->aa_dev->mem[0].addr == USBUH1_EHCI_ADDR) {
/* enable usb port power */
switch (board_id)
{
case BOARD_ID_IMX6_PHYFLEX:
imxgpio_set_dir(EHCI_PHYFLEX_USB_H1_PWR, IMXGPIO_DIR_OUT);
delay(10);
imxgpio_set_bit(EHCI_PHYFLEX_USB_H1_PWR);
delay(10);
break;
case BOARD_ID_IMX6_CUBOXI:
case BOARD_ID_IMX6_HUMMINGBOARD:
imxgpio_set_bit(EHCI_HUMMINGBOARD_USB_H1_PWR);
imxgpio_set_dir(EHCI_HUMMINGBOARD_USB_H1_PWR, IMXGPIO_DIR_OUT);
delay(10);
break;
case BOARD_ID_IMX6_SABRELITE:
imxgpio_clear_bit(EHCI_NITROGEN6X_USB_HUB_RST);
imxgpio_set_dir(EHCI_NITROGEN6X_USB_HUB_RST, IMXGPIO_DIR_OUT);
delay(1000 * 2);
imxgpio_set_bit(EHCI_NITROGEN6X_USB_HUB_RST);
delay(10);
break;
case BOARD_ID_IMX6_SABRESD:
imxgpio_set_bit(EHCI_SABRESD_USB_PWR);
imxgpio_set_dir(EHCI_SABRESD_USB_PWR, IMXGPIO_DIR_OUT);
delay(10);
break;
case BOARD_ID_IMX6_UTILITE:
imxgpio_clear_bit(EHCI_UTILITE_USB_HUB_RST);
imxgpio_set_dir(EHCI_UTILITE_USB_HUB_RST, IMXGPIO_DIR_OUT);
delay(10);
imxgpio_set_bit(EHCI_UTILITE_USB_HUB_RST);
delay(1000);
break;
}
/* disable the carger detection, else signal on DP will be poor */
imxccm_disable_usb2_chrg_detect();
/* power host 1 */
imxccm_enable_pll_usb2();
/* over current and polarity setting */
bus_space_write_4(sc->sc.iot, sc->nc_ioh, USBNC_USB_UH1_CTRL,
bus_space_read_4(sc->sc.iot, sc->nc_ioh, USBNC_USB_UH1_CTRL) |
(USBNC_USB_UH1_CTRL_OVER_CUR_POL | USBNC_USB_UH1_CTRL_OVER_CUR_DIS));
} else if (aa->aa_dev->mem[0].addr == USBOTG_EHCI_ADDR) {
/* enable usb port power */
switch (board_id)
{
case BOARD_ID_IMX6_CUBOXI:
case BOARD_ID_IMX6_HUMMINGBOARD:
imxgpio_set_dir(EHCI_HUMMINGBOARD_USB_OTG_PWR, IMXGPIO_DIR_OUT);
imxgpio_set_bit(EHCI_HUMMINGBOARD_USB_OTG_PWR);
delay(10);
break;
}
/* disable the carger detection, else signal on DP will be poor */
imxccm_disable_usb1_chrg_detect();
/* power host 0 */
imxccm_enable_pll_usb1();
/* over current and polarity setting */
bus_space_write_4(sc->sc.iot, sc->nc_ioh, USBNC_USB_OTG_CTRL,
bus_space_read_4(sc->sc.iot, sc->nc_ioh, USBNC_USB_OTG_CTRL) |
(USBNC_USB_OTG_CTRL_OVER_CUR_POL | USBNC_USB_OTG_CTRL_OVER_CUR_DIS));
}
bus_space_write_4(sc->sc.iot, sc->ph_ioh, USBPHY_CTRL_CLR,
USBPHY_CTRL_CLKGATE);
/* Disable interrupts, so we don't get any spurious ones. */
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
/* Stop then Reset */
uint32_t val = EOREAD4(&sc->sc, EHCI_USBCMD);
val &= ~EHCI_CMD_RS;
EOWRITE4(&sc->sc, EHCI_USBCMD, val);
while (EOREAD4(&sc->sc, EHCI_USBCMD) & EHCI_CMD_RS)
;
val = EOREAD4(&sc->sc, EHCI_USBCMD);
val |= EHCI_CMD_HCRESET;
EOWRITE4(&sc->sc, EHCI_USBCMD, val);
while (EOREAD4(&sc->sc, EHCI_USBCMD) & EHCI_CMD_HCRESET)
;
/* Reset USBPHY module */
bus_space_write_4(sc->sc.iot, sc->ph_ioh, USBPHY_CTRL_SET, USBPHY_CTRL_SFTRST);
delay(10);
/* Remove CLKGATE and SFTRST */
bus_space_write_4(sc->sc.iot, sc->ph_ioh, USBPHY_CTRL_CLR,
USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
delay(10);
/* Power up the PHY */
bus_space_write_4(sc->sc.iot, sc->ph_ioh, USBPHY_PWD, 0);
/* enable FS/LS device */
bus_space_write_4(sc->sc.iot, sc->ph_ioh, USBPHY_CTRL_SET,
USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
/* set host mode */
EWRITE4(&sc->sc, EHCI_USBMODE,
EREAD4(&sc->sc, EHCI_USBMODE) | EHCI_USBMODE_HOST);
/* set to UTMI mode */
EOWRITE4(&sc->sc, EHCI_PORTSC(1),
EOREAD4(&sc->sc, EHCI_PORTSC(1)) & ~EHCI_PS_PTS_UTMI_MASK);
sc->sc_ih = arm_intr_establish(aa->aa_dev->irq[0], IPL_USB,
ehci_intr, &sc->sc, devname);
if (sc->sc_ih == NULL) {
printf(": unable to establish interrupt\n");
goto mem3;
}
strlcpy(sc->sc.sc_vendor, "i.MX6", sizeof(sc->sc.sc_vendor));
r = ehci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
goto intr;
}
config_found(self, &sc->sc.sc_bus, usbctlprint);
goto out;
intr:
arm_intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
mem3:
bus_space_unmap(sc->sc.iot, sc->nc_ioh, aa->aa_dev->mem[3].addr);
mem2:
bus_space_unmap(sc->sc.iot, sc->ph_ioh, aa->aa_dev->mem[2].addr);
mem1:
bus_space_unmap(sc->sc.iot, sc->uh_ioh, aa->aa_dev->mem[1].addr);
mem0:
bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
sc->sc.sc_size = 0;
out:
return;
}
void
imxehci_attach(struct device *parent, struct device *self, void *aux)
{
struct imxehci_softc *sc = (struct imxehci_softc *)self;
struct ehci_softc *esc;
struct armv7_attach_args *aa = aux;
struct fdt_memory hmem, pmem, mmem;
int irq, r;
sc->iot = aa->aa_iot;
sc->sc_dmat = aa->aa_dmat;
if (aa->aa_node) {
uint32_t ints[3];
void *node;
if (fdt_get_memory_address(aa->aa_node, 0, &hmem))
panic("%s: could not extract memory data from FDT",
__func__);
node = fdt_find_node_by_phandle_prop(aa->aa_node, "fsl,usbphy");
if (node == NULL || fdt_get_memory_address(node, 0, &pmem))
panic("%s: could not extract phy data from FDT",
__func__);
node = fdt_find_node_by_phandle_prop(aa->aa_node, "fsl,usbmisc");
if (node == NULL || fdt_get_memory_address(node, 0, &mmem))
panic("%s: could not extract phy data from FDT",
__func__);
/* TODO: Add interrupt FDT API. */
if (fdt_node_property_ints(aa->aa_node, "interrupts",
ints, 3) != 3)
panic("%s: could not extract interrupt data from FDT",
__func__);
irq = ints[1];
} else {
hmem.addr = aa->aa_dev->mem[0].addr;
hmem.size = aa->aa_dev->mem[0].size;
pmem.addr = aa->aa_dev->mem[1].addr;
pmem.size = aa->aa_dev->mem[1].size;
mmem.addr = aa->aa_dev->mem[2].addr;
mmem.size = aa->aa_dev->mem[2].size;
irq = aa->aa_dev->irq[0];
}
/* Map I/O space */
if (bus_space_map(sc->iot, hmem.addr, hmem.size, 0, &sc->uh_ioh)) {
printf(": cannot map mem space\n");
goto hmem;
}
sc->ioh = sc->uh_ioh + 0x100;
sc->sc_size = hmem.size;
if (bus_space_map(sc->iot, pmem.addr, pmem.size, 0, &sc->ph_ioh)) {
printf(": cannot map mem space\n");
goto pmem;
}
if (bus_space_map(sc->iot, mmem.addr, mmem.size, 0, &sc->nc_ioh)) {
printf(": cannot map mem space\n");
goto mmem;
}
clk_enable(clk_get("usboh3"));
delay(1000);
if (hmem.addr == USBUH1_ADDR) {
/* enable usb port power */
switch (board_id)
{
case BOARD_ID_IMX6_CUBOXI:
case BOARD_ID_IMX6_HUMMINGBOARD:
imxgpio_set_bit(EHCI_HUMMINGBOARD_USB_H1_PWR);
imxgpio_set_dir(EHCI_HUMMINGBOARD_USB_H1_PWR, IMXGPIO_DIR_OUT);
delay(10);
break;
case BOARD_ID_IMX6_SABRELITE:
imxgpio_clear_bit(EHCI_NITROGEN6X_USB_HUB_RST);
imxgpio_set_dir(EHCI_NITROGEN6X_USB_HUB_RST, IMXGPIO_DIR_OUT);
delay(1000 * 2);
imxgpio_set_bit(EHCI_NITROGEN6X_USB_HUB_RST);
delay(10);
break;
case BOARD_ID_IMX6_SABRESD:
imxgpio_set_bit(EHCI_SABRESD_USB_PWR);
imxgpio_set_dir(EHCI_SABRESD_USB_PWR, IMXGPIO_DIR_OUT);
delay(10);
break;
case BOARD_ID_IMX6_UTILITE:
imxgpio_clear_bit(EHCI_UTILITE_USB_HUB_RST);
imxgpio_set_dir(EHCI_UTILITE_USB_HUB_RST, IMXGPIO_DIR_OUT);
delay(10);
imxgpio_set_bit(EHCI_UTILITE_USB_HUB_RST);
delay(1000);
break;
}
/* disable the carger detection, else signal on DP will be poor */
imxccm_disable_usb2_chrg_detect();
/* power host 1 */
clk_enable(clk_get("pll7_usb_host"));
clk_enable(clk_get("usbphy2_gate"));
/* over current and polarity setting */
bus_space_write_4(sc->iot, sc->nc_ioh, USBNC_USB_UH1_CTRL,
bus_space_read_4(sc->iot, sc->nc_ioh, USBNC_USB_UH1_CTRL) |
(USBNC_USB_UH1_CTRL_OVER_CUR_POL | USBNC_USB_UH1_CTRL_OVER_CUR_DIS));
} else if (hmem.addr == USBOTG_ADDR) {
/* enable usb port power */
switch (board_id)
{
case BOARD_ID_IMX6_CUBOXI:
case BOARD_ID_IMX6_HUMMINGBOARD:
imxgpio_set_bit(EHCI_HUMMINGBOARD_USB_OTG_PWR);
imxgpio_set_dir(EHCI_HUMMINGBOARD_USB_OTG_PWR, IMXGPIO_DIR_OUT);
delay(10);
break;
}
/* disable the carger detection, else signal on DP will be poor */
imxccm_disable_usb1_chrg_detect();
/* power host 0 */
clk_enable(clk_get("pll3_usb_otg"));
clk_enable(clk_get("usbphy1_gate"));
/* over current and polarity setting */
bus_space_write_4(sc->iot, sc->nc_ioh, USBNC_USB_OTG_CTRL,
bus_space_read_4(sc->iot, sc->nc_ioh, USBNC_USB_OTG_CTRL) |
(USBNC_USB_OTG_CTRL_OVER_CUR_POL | USBNC_USB_OTG_CTRL_OVER_CUR_DIS));
}
bus_space_write_4(sc->iot, sc->ph_ioh, USBPHY_CTRL_CLR,
USBPHY_CTRL_CLKGATE);
/* Disable interrupts, so we don't get any spurious ones. */
sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
EOWRITE2(sc, EHCI_USBINTR, 0);
/* Stop then Reset */
uint32_t val = EOREAD4(sc, EHCI_USBCMD);
val &= ~EHCI_CMD_RS;
EOWRITE4(sc, EHCI_USBCMD, val);
while (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_RS)
;
val = EOREAD4(sc, EHCI_USBCMD);
val |= EHCI_CMD_HCRESET;
EOWRITE4(sc, EHCI_USBCMD, val);
while (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET)
;
/* Reset USBPHY module */
bus_space_write_4(sc->iot, sc->ph_ioh, USBPHY_CTRL_SET, USBPHY_CTRL_SFTRST);
delay(10);
/* Remove CLKGATE and SFTRST */
bus_space_write_4(sc->iot, sc->ph_ioh, USBPHY_CTRL_CLR,
USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
delay(10);
/* Power up the PHY */
bus_space_write_4(sc->iot, sc->ph_ioh, USBPHY_PWD, 0);
/* enable FS/LS device */
bus_space_write_4(sc->iot, sc->ph_ioh, USBPHY_CTRL_SET,
USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
/* set host mode */
EWRITE4(sc, EHCI_USBMODE,
EREAD4(sc, EHCI_USBMODE) | EHCI_USBMODE_HOST);
/* set to UTMI mode */
EOWRITE4(sc, EHCI_PORTSC(1),
EOREAD4(sc, EHCI_PORTSC(1)) & ~EHCI_PS_PTS_UTMI_MASK);
printf("\n");
if ((esc = (struct ehci_softc *)config_found(self, NULL, NULL)) == NULL)
goto mmem;
esc->iot = sc->iot;
esc->ioh = sc->ioh;
esc->sc_bus.dmatag = sc->sc_dmat;
esc->sc_offs = sc->sc_offs;
sc->sc_ih = arm_intr_establish(irq, IPL_USB,
ehci_intr, esc, esc->sc_bus.bdev.dv_xname);
if (sc->sc_ih == NULL) {
printf(": unable to establish interrupt\n");
return;
}
strlcpy(esc->sc_vendor, "i.MX6", sizeof(esc->sc_vendor));
r = ehci_init(esc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n",
esc->sc_bus.bdev.dv_xname, r);
goto intr;
}
printf("\n");
config_found((struct device *)esc, &esc->sc_bus, usbctlprint);
goto out;
intr:
arm_intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
mmem:
bus_space_unmap(sc->iot, sc->nc_ioh, mmem.size);
pmem:
bus_space_unmap(sc->iot, sc->ph_ioh, pmem.size);
hmem:
bus_space_unmap(sc->iot, sc->uh_ioh, sc->sc_size);
sc->sc_size = 0;
out:
return;
}
