Ejemplo n.º 1
0
    SLCR_REG(MIO_PIN_44) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(MIO_PIN_45) = MIO_L3_SEL(0x4) | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(MIO_PIN_47) = MIO_TRI_ENABLE | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(MIO_PIN_48) = MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(MIO_PIN_49) = MIO_TRI_ENABLE | MIO_L3_SEL(0x7) | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(MIO_PIN_52) = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(MIO_PIN_53) = MIO_L3_SEL(0x4) | MIO_IO_TYPE_LVCMOS18;
    SLCR_REG(SD0_WP_CD_SEL) = SDIO0_WP_SEL(0x37) | SDIO0_CD_SEL(0x2F);

    zynq_slcr_lock();

    return 0;
}

static const unsigned long ps7_pll_init_data_3_0[] = {
    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
Ejemplo n.º 2
0
// SPDX-License-Identifier: GPL-2.0+
/*
 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
 * (c) Copyright 2016 Topic Embedded Products.
 */

#include <asm/arch/ps7_init_gpl.h>

static unsigned long ps7_pll_init_data_3_0[] = {
	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00030000U),
	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
Ejemplo n.º 3
0
/*
 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <asm/arch/ps7_init_gpl.h>

static unsigned long ps7_pll_init_data_3_0[] = {
	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
Ejemplo n.º 4
0
// SPDX-License-Identifier: GPL-2.0+
/*
 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
 */

#include <asm/arch/ps7_init_gpl.h>

static unsigned long ps7_pll_init_data_3_0[] = {
	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
	EMIT_MASKPOLL(0xF800010C, 0x00000004U),