static void setup_rcrb(const int peg_enabled)
{
/*\ RCRB setup: Egress Port \*/
/* Set component ID of MCH (1). */
EPBAR8(EPESD + 2) = 1;
/* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
if (peg_enabled)
/* Link2: link_valid. */
EPBAR8(EPLE2D) |= (1 << 0); /* link valid */
/*\ RCRB setup: DMI Port \*/
/* Set component ID of MCH (1). */
DMIBAR8(DMIESD + 2) = 1;
/* Link1: target port 0, component id 2 (ICH), link valid. */
DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0);
DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
/* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR;
}
static void init_egress(void)
{
/* VC0: TC0 only */
EPBAR8(0x14) = 1;
EPBAR8(0x4) = 1;
/* VC1: ID1, TC7 */
EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
EPBAR8(0x20) = 1 << 7;
/* VC1: enable */
EPBAR32(0x20) |= 1 << 31;
while ((EPBAR8(0x26) & 2) != 0) ;
printk(BIOS_DEBUG, "Done EP loop\n");
}
static void init_egress(void)
{
/* VC0: TC0 only */
EPBAR8(0x14) &= 1;
EPBAR8(0x4) = (EPBAR8(0x4) & ~7) | 1;
/* VC1: isoch */
EPBAR32(0x28) = 0x0a0a0a0a;
EPBAR32(0x1c) = (EPBAR32(0x1c) & ~(127 << 16)) | (0x0a << 16);
/* VC1: ID1, TC7 */
EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
EPBAR8(0x20) = (EPBAR8(0x20) & 1) | (1 << 7);
/* VC1 ARB table: setup and enable */
EPBAR32(0x100) = 0x55555555;
EPBAR32(0x104) = 0x55555555;
EPBAR32(0x108) = 0x55555555;
EPBAR32(0x10c) = 0x55555555;
EPBAR32(0x110) = 0x55555555;
EPBAR32(0x114) = 0x55555555;
EPBAR32(0x118) = 0x55555555;
EPBAR32(0x11c) = 0x00005555;
EPBAR32(0x20) |= 1 << 16;
while ((EPBAR8(0x26) & 1) != 0) ;
/* VC1: enable */
EPBAR32(0x20) |= 1 << 31;
while ((EPBAR8(0x26) & 2) != 0) ;
}
static void init_egress(void)
{
u32 reg32;
/* VC0: TC0 only */
EPBAR8(0x14) = 1;
EPBAR8(0x4) = 1;
switch (MCHBAR32(0xc00) & 0x7) {
case 0x0:
/* FSB 1066 */
EPBAR32(0x2c) = 0x0001a6db;
break;
case 0x2:
/* FSB 800 */
EPBAR32(0x2c) = 0x00014514;
break;
default:
case 0x4:
/* FSB 1333 */
EPBAR32(0x2c) = 0x00022861;
break;
}
EPBAR32(0x28) = 0x0a0a0a0a;
EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2;
EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000;
MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7;
/* VC1: ID1, TC7 */
reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xfe) | (1 << 7);
EPBAR32(0x20) = reg32;
/* Init VC1 port arbitration table */
EPBAR32(0x100) = 0x001000001;
EPBAR32(0x104) = 0x000040000;
EPBAR32(0x108) = 0x000001000;
EPBAR32(0x10c) = 0x000000040;
EPBAR32(0x110) = 0x001000001;
EPBAR32(0x114) = 0x000040000;
EPBAR32(0x118) = 0x000001000;
EPBAR32(0x11c) = 0x000000040;
/* Load table */
reg32 = EPBAR32(0x20) | (1 << 16);
EPBAR32(0x20) = reg32;
asm("nop");
EPBAR32(0x20) = reg32;
/* Wait for table load */
while ((EPBAR8(0x26) & (1 << 0)) != 0);
/* VC1: enable */
EPBAR32(0x20) |= 1 << 31;
/* Wait for VC1 */
while ((EPBAR8(0x26) & (1 << 1)) != 0);
printk(BIOS_DEBUG, "Done Egress Port\n");
}
