//***************************************************************************** // //! \brief Initializes the SPI Slave block. //! //! Upon successful initialization of the SPI slave block, this function will //! have initailized the slave block, but the SPI Slave block still remains //! disabled and must be enabled with EUSCI_B_SPI_enable() //! //! \param baseAddress is the base address of the EUSCI_B_SPI Slave module. //! \param msbFirst controls the direction of the receive and transmit shift //! register. //! Valid values are: //! - \b EUSCI_B_SPI_MSB_FIRST //! - \b EUSCI_B_SPI_LSB_FIRST [Default] //! \param clockPhase is clock phase select. //! Valid values are: //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT //! [Default] //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT //! \param clockPolarity is clock polarity select //! Valid values are: //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] //! \param spiMode is SPI mode select //! Valid values are: //! - \b EUSCI_B_SPI_3PIN //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW //! //! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. //! //! \return STATUS_SUCCESS // //***************************************************************************** bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode) { ASSERT( (EUSCI_B_SPI_MSB_FIRST == msbFirst) || (EUSCI_B_SPI_LSB_FIRST == msbFirst)); ASSERT( (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase)); ASSERT( (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity)); ASSERT( (EUSCI_B_SPI_3PIN == spiMode) || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode) || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode)); //Disable USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1; //Reset OFS_UCBxCTLW0 register EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3)) | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode); return true; }
void DWire::_initSlave( void ) { // Init the pins MAP_GPIO_setAsPeripheralModuleFunctionInputPin( modulePort, modulePins, GPIO_PRIMARY_MODULE_FUNCTION ); // initialise driverlib MAP_I2C_initSlave( module, slaveAddress, EUSCI_B_I2C_OWN_ADDRESS_OFFSET0, EUSCI_B_I2C_OWN_ADDRESS_ENABLE ); // Enable the module and enable interrupts MAP_I2C_enableModule( module ); MAP_I2C_clearInterruptFlag( module, EUSCI_B_I2C_RECEIVE_INTERRUPT0 | EUSCI_B_I2C_STOP_INTERRUPT | EUSCI_B_I2C_TRANSMIT_INTERRUPT0 | EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT ); MAP_I2C_enableInterrupt( module, EUSCI_B_I2C_RECEIVE_INTERRUPT0 | EUSCI_B_I2C_STOP_INTERRUPT | EUSCI_B_I2C_TRANSMIT_INTERRUPT0 | EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT ); /* Enable the clock low timeout */ EUSCI_B_CMSIS( module )->CTLW1 = (EUSCI_B_CMSIS( module )->CTLW1 & ~EUSCI_B_CTLW1_CLTO_MASK) | 0xC0; MAP_Interrupt_enableInterrupt( intModule ); MAP_Interrupt_enableMaster( ); }
bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance, uint8_t *txData, uint32_t timeout) { uint32_t timeout2 = timeout; ASSERT(timeout > 0); //Send stop condition. BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1; //Wait for Stop to finish while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS) && --timeout) ; //Check if transfer timed out if (timeout == 0) return false; // Wait for RX buffer while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS)) && --timeout2) ; //Check if transfer timed out if (timeout2 == 0) return false; //Capture data from receive buffer after setting stop bit due to //MSP430 I2C critical timing. *txData = (EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF); return true; }
void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData) { //Store current TXIE status uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE; //Disable transmit interrupt enable BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0; //Send start condition. EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT; //Poll for transmit interrupt flag. while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) ; //Send single byte data. EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData; //Poll for transmit interrupt flag. while (!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) ; //Send stop condition. EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTXSTP; //Clear transmit interrupt flag before enabling interrupt again EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(UCTXIFG); //Reinstate transmit interrupt enable EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus; }
void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode) { ASSERT( (EUSCI_B_I2C_TRANSMIT_MODE == mode) || (EUSCI_B_I2C_RECEIVE_MODE == mode)); EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r = (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode; }
//***************************************************************************** // //! \brief Initializes the SPI Master clock. At the end of this function call, //! SPI module is left enabled. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! \param clockSourceFrequency is the frequency of the slected clock source //! \param desiredSpiClock is the desired clock rate for SPI communication //! //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress, uint32_t clockSourceFrequency, uint32_t desiredSpiClock) { //Disable the USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1; EUSCI_B_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency / desiredSpiClock); //Reset the UCSWRST bit to enable the USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0; }
//***************************************************************************** // //! \brief Selects 4Pin Functionality //! //! This function should be invoked only in 4-wire mode. Invoking this function //! has no effect in 3-wire mode. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! \param select4PinFunctionality selects 4 pin functionality //! Valid values are: //! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS //! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE //! //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress, uint8_t select4PinFunctionality) { ASSERT( (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS == select4PinFunctionality) || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE == select4PinFunctionality)); EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r & ~UCSTEM) | select4PinFunctionality; }
uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance) { //Polling RXIFG0 if RXIE is not enabled if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCRXIE0_OFS)) { while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG0_OFS)) ; } //Read a byte. return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF; }
void I2C_masterSendMultiByteStop(uint32_t moduleInstance) { //If interrupts are not used, poll for flags if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS)) { //Poll for transmit interrupt flag. while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS)) ; } //Send stop condition. BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1; }
void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData) { //If interrupts are not used, poll for flags if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS)) { //Poll for transmit interrupt flag. while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS)) ; } //Send single byte data. EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData; }
uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance) { //Set USCI in Receive mode BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTR_OFS) = 0; //Send start EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= (UCTXSTT + UCTXSTP); //Poll for receive interrupt flag. while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCRXIFG_OFS)) ; //Send single byte data. return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF; }
uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance) { //Send stop condition. BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1; //Wait for Stop to finish while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCTXSTP_OFS)) { // Wait for RX buffer while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG, UCRXIFG_OFS)) ; } /* Capture data from receive buffer after setting stop bit due to MSP430 I2C critical timing. */ return EUSCI_B_CMSIS(moduleInstance)->rRXBUF.b.bRXBUF; }
//***************************************************************************** // //! \brief Clears the selected SPI interrupt status flag. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! \param mask is the masked interrupt flag to be cleared. //! Mask value is the logical OR of any of the following: //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT //! //! Modified bits of \b UCAxIFG register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask) { ASSERT( !(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); EUSCI_B_CMSIS(baseAddress)->rIFG.r &= ~mask; }
//***************************************************************************** // //! \brief Gets the current SPI interrupt status. //! //! This returns the interrupt status for the SPI module based on which flag is //! passed. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! \param mask is the masked interrupt flag status to be returned. //! Mask value is the logical OR of any of the following: //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT //! //! \return Logical OR of any of the following: //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT //! \n indicating the status of the masked interrupts // //***************************************************************************** uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask) { ASSERT( !(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); return EUSCI_B_CMSIS(baseAddress)->rIFG.r & mask; }
//***************************************************************************** // //! \brief Disables individual SPI interrupt sources. //! //! Disables the indicated SPI interrupt sources. Only the sources that are //! enabled can be reflected to the processor interrupt; disabled sources have //! no effect on the processor. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! \param mask is the bit mask of the interrupt sources to be disabled. //! Mask value is the logical OR of any of the following: //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT //! //! Modified bits of \b UCAxIE register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask) { ASSERT( !(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); EUSCI_B_CMSIS(baseAddress)->rIE.r &= ~mask; }
bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance, uint8_t txData, uint32_t timeout) { uint16_t txieStatus; uint32_t timeout2 = timeout; ASSERT(timeout > 0); //Store current TXIE status txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE; //Disable transmit interrupt enable BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r,UCTXIE_OFS) = 0; //Send start condition. EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT; //Poll for transmit interrupt flag. while ((!(EUSCI_B_CMSIS(moduleInstance)->rIFG.r & UCTXIFG)) && --timeout) ; //Check if transfer timed out if (timeout == 0) return false; //Send single byte data. EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData; //Poll for transmit interrupt flag. while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS)) && --timeout2) ; //Check if transfer timed out if (timeout2 == 0) return false; //Send stop condition. BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1; //Clear transmit interrupt flag before enabling interrupt again BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r,UCTXIFG_OFS) = 0; //Reinstate transmit interrupt enable EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus; return true; }
void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress, uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable) { ASSERT( (EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset) || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset) || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset) || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset)); /* Disable the USCI module */ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1; /* Clear USCI master mode */ EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r = (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & (~UCMST)) | (UCMODE_3 + UCSYNC); /* Set up the slave address. */ HWREG16(moduleInstance + OFS_UCB0I2COA0 + slaveAddressOffset) = slaveAddress + slaveOwnAddressEnable; }
bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance, uint8_t txData, uint32_t timeout) { ASSERT(timeout > 0); //If interrupts are not used, poll for flags if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS)) { //Poll for transmit interrupt flag. while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS)) && --timeout) ; //Check if transfer timed out if (timeout == 0) return false; } //Send single byte data. EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData; return true; }
bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance, uint32_t timeout) { ASSERT(timeout > 0); //If interrupts are not used, poll for flags if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS)) { //Poll for transmit interrupt flag. while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS)) && --timeout) ; //Check if transfer timed out if (timeout == 0) return false; } //Send stop condition. BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCTXSTP_OFS) = 1; return 0x01; }
void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config) { uint16_t preScalarValue; ASSERT( (EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource) || (EUSCI_B_I2C_CLOCKSOURCE_SMCLK == config->selectClockSource)); ASSERT( (EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate) || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)); ASSERT( (EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration) || (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG == config->autoSTOPGeneration) || (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD == config->autoSTOPGeneration)); /* Disable the USCI module and clears the other bits of control register */ BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r,UCSWRST_OFS) = 1; /* Configure Automatic STOP condition generation */ EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r = (EUSCI_B_CMSIS(moduleInstance)->rCTLW1.r & ~UCASTP_M) | (config->autoSTOPGeneration); /* Byte Count Threshold */ EUSCI_B_CMSIS(moduleInstance)->rTBCNT.r = config->byteCounterThreshold; /* * Configure as I2C master mode. * UCMST = Master mode * UCMODE_3 = I2C mode * UCSYNC = Synchronous mode */ EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r = (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r & ~UCSSEL_M) | (config->selectClockSource | UCMST | UCMODE_3 | UCSYNC | UCSWRST); /* * Compute the clock divider that achieves the fastest speed less than or * equal to the desired speed. The numerator is biased to favor a larger * clock divider so that the resulting clock is always less than or equal * to the desired clock, never greater. */ preScalarValue = (uint16_t) (config->i2cClk / config->dataRate); EUSCI_B_CMSIS(moduleInstance)->rBRW = preScalarValue; }
//***************************************************************************** // //! \brief Changes the SPI colock phase and polarity. At the end of this //! function call, SPI module is left enabled. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! \param clockPhase is clock phase select. //! Valid values are: //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT //! [Default] //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT //! \param clockPolarity is clock polarity select //! Valid values are: //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] //! //! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0 //! register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress, uint16_t clockPhase, uint16_t clockPolarity) { ASSERT( (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity)); ASSERT( (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase)); //Disable the USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1; EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity); //Reset the UCSWRST bit to enable the USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0; }
uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance) { if (is_A_Module(moduleInstance)) { return SPI_getInterruptStatus(moduleInstance, EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT) & EUSCI_A_CMSIS(moduleInstance)->IE; } else { return SPI_getInterruptStatus(moduleInstance, EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT) & EUSCI_B_CMSIS(moduleInstance)->IE; } }
void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask) { ASSERT( 0x00 == (mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + EUSCI_B_I2C_START_INTERRUPT + EUSCI_B_I2C_NAK_INTERRUPT + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); //Clear the I2C interrupt source. EUSCI_B_CMSIS(moduleInstance)->rIFG.r &= ~(mask); }
uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask) { ASSERT( 0x00 == (mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + EUSCI_B_I2C_START_INTERRUPT + EUSCI_B_I2C_NAK_INTERRUPT + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); //Return the interrupt status of the request masked bit. return EUSCI_B_CMSIS(moduleInstance)->rIFG.r & mask; }
void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask) { ASSERT( 0x00 == (mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + EUSCI_B_I2C_START_INTERRUPT + EUSCI_B_I2C_NAK_INTERRUPT + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); //Disable the interrupt masked bit EUSCI_B_CMSIS(moduleInstance)->rIE.r &= ~(mask); }
void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData) { //Store current transmit interrupt enable uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->rIE.r & UCTXIE; //Disable transmit interrupt enable BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIE.r, UCTXIE_OFS) = 0; //Send start condition. EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r |= UCTR + UCTXSTT; //Poll for transmit interrupt flag. while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rIFG.r, UCTXIFG_OFS)) ; //Send single byte data. EUSCI_B_CMSIS(moduleInstance)->rTXBUF.r = txData; //Reinstate transmit interrupt enable EUSCI_B_CMSIS(moduleInstance)->rIE.r |= txieStatus; }
uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance) { return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF; }
//***************************************************************************** // //! \brief Indicates whether or not the SPI bus is busy. //! //! This function returns an indication of whether or not the SPI bus is //! busy.This function checks the status of the bus via UCBBUSY bit //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! //! \return true if busy, false otherwise // //***************************************************************************** bool EUSCI_B_SPI_isBusy(uint32_t baseAddress) { //Return the bus busy status. return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS); }
//***************************************************************************** // //! \brief Disables the SPI block. //! //! This will disable operation of the SPI block. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_disable(uint32_t baseAddress) { //Set the UCSWRST bit to disable the USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1; }
//***************************************************************************** // //! \brief Enables the SPI block. //! //! This will enable operation of the SPI block. //! //! \param baseAddress is the base address of the EUSCI_B_SPI module. //! //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. //! //! \return None // //***************************************************************************** void EUSCI_B_SPI_enable(uint32_t baseAddress) { //Reset the UCSWRST bit to enable the USCI Module BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0; }