void map_init_217(void) {
EXTCL_CPU_WR_MEM(217);
EXTCL_SAVE_MAPPER(217);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &m217;
mapper.internal_struct_size[0] = sizeof(m217);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
m217.reg[0] = 0x00;
m217.reg[1] = 0xFF;
m217.reg[2] = 0x03;
}
m217.reg[3] = FALSE;
m217.prg_8k_bank[0] = 0;
m217.prg_8k_bank[1] = 1;
m217.prg_8k_bank[2] = info.prg.rom.max.banks_8k_before_last;
m217.prg_8k_bank[3] = info.prg.rom.max.banks_8k;
info.mapper.extend_wr = TRUE;
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_121(void) {
EXTCL_CPU_WR_MEM(121);
EXTCL_CPU_RD_MEM(121);
EXTCL_SAVE_MAPPER(121);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &m121;
mapper.internal_struct_size[0] = sizeof(m121);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&m121, 0x00, sizeof(m121));
memset(&mmc3, 0x00, sizeof(mmc3));
m121.bck[0] = mapper.rom_map_to[0];
m121.bck[1] = mapper.rom_map_to[2];
}
memset(&irqA12, 0x00, sizeof(irqA12));
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_91(void) {
EXTCL_CPU_WR_MEM(91);
EXTCL_SAVE_MAPPER(91);
EXTCL_PPU_256_TO_319(91);
mapper.internal_struct[0] = (BYTE *) &m91;
mapper.internal_struct_size[0] = sizeof(m91);
memset(&m91, 0x00, sizeof(m91));
info.mapper.extend_wr = TRUE;
}
void map_init_SC_127(void) {
EXTCL_CPU_WR_MEM(SC_127);
EXTCL_CPU_RD_MEM(SC_127);
EXTCL_SAVE_MAPPER(SC_127);
EXTCL_PPU_256_TO_319(SC_127);
mapper.internal_struct[0] = (BYTE *) &sc127;
mapper.internal_struct_size[0] = sizeof(sc127);
memset(&sc127, 0x00, sizeof(sc127));
info.prg.ram.banks_8k_plus = 1;
}
void map_init_BMC411120C(void) {
EXTCL_CPU_WR_MEM(BMC411120C);
EXTCL_SAVE_MAPPER(BMC411120C);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &bmc411120c;
mapper.internal_struct_size[0] = sizeof(bmc411120c);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
memset(&bmc411120c, 0x00, sizeof(bmc411120c));
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
{
BYTE i;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
if (i < 4) {
bmc411120c.prg_map[i] = mapper.rom_map_to[i];
}
bmc411120c.chr_map[i] = i;
}
}
if (info.reset >= HARD) {
bmc411120c_reset = 0;
} else if (info.reset == RESET) {
bmc411120c_reset ^= 0x04;
}
bmc411120c_update_prg();
bmc411120c_update_chr();
info.mapper.extend_wr = TRUE;
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_182(void) {
EXTCL_CPU_WR_MEM(182);
EXTCL_SAVE_MAPPER(MMC3);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &mmc3;
mapper.internal_struct_size[0] = sizeof(mmc3);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
}
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_SL1632(void) {
EXTCL_CPU_WR_MEM(SL1632);
EXTCL_SAVE_MAPPER(SL1632);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &sl1632;
mapper.internal_struct_size[0] = sizeof(sl1632);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
memset(&sl1632, 0x00, sizeof(sl1632));
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
{
BYTE i;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
if (i < 4) {
sl1632.mmc3.prg_map[i] = mapper.rom_map_to[i];
}
sl1632.mmc3.chr_map[i] = sl1632.chr_map[i] = i;
}
sl1632.prg_map[0] = mapper.rom_map_to[0];
sl1632.prg_map[1] = mapper.rom_map_to[1];
}
info.mapper.extend_wr = TRUE;
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_254(void) {
EXTCL_CPU_WR_MEM(254);
EXTCL_CPU_RD_MEM(254);
EXTCL_SAVE_MAPPER(254);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &m254;
mapper.internal_struct_size[0] = sizeof(m254);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
memset(&m254, 0x00, sizeof(m254));
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
irqA12.present = TRUE;
irqA12_delay = 1;
}
void map_init_Waixing(BYTE model) {
switch (model) {
case WPSX:
EXTCL_CPU_WR_MEM(Waixing_PSx);
map_prg_rom_8k(4, 0, 0);
break;
case WTB:
EXTCL_CPU_WR_MEM(Waixing_type_B);
EXTCL_SAVE_MAPPER(Waixing_type_B);
EXTCL_WR_CHR(Waixing_type_B);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i;
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
waixing.chr_map[i] = i;
}
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case WTA:
case WTC:
case WTD:
case WTE:
if (model == WTA) {
min = 0x08;
max = 0x09;
} else if (model == WTC) {
min = 0x08;
max = 0x0B;
} else if (model == WTD) {
min = 0x00;
max = 0x01;
} else if (model == WTE) {
min = 0x00;
max = 0x03;
}
EXTCL_CPU_WR_MEM(Waixing_type_ACDE);
EXTCL_SAVE_MAPPER(Waixing_type_ACDE);
EXTCL_WR_CHR(Waixing_type_ACDE);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i;
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
waixing.chr_map[i] = i;
if ((waixing.chr_map[i] >= min) && (waixing.chr_map[i] <= max)) {
chr.bank_1k[i] = &chr.extra.data[(waixing.chr_map[i] - min) << 10];
}
}
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case WTG:
EXTCL_CPU_WR_MEM(Waixing_type_G);
EXTCL_SAVE_MAPPER(Waixing_type_G);
EXTCL_WR_CHR(Waixing_type_G);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i;
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
waixing.chr_map[i] = i;
if (waixing.chr_map[i] < 8) {
chr.bank_1k[i] = &chr.extra.data[waixing.chr_map[i] << 10];
}
}
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case WTH:
EXTCL_CPU_WR_MEM(Waixing_type_H);
EXTCL_SAVE_MAPPER(Waixing_type_H);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
EXTCL_UPDATE_R2006(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
{
BYTE i, value;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
for (i = 0; i < 8; i++) {
if (i < 4) {
waixing.prg_map[i] = mapper.rom_map_to[i];
}
waixing.chr_map[i] = i;
if (mapper.write_vram) {
chr.bank_1k[i] = &chr.extra.data[waixing.chr_map[i] << 10];
}
}
waixing_type_H_prg_8k_update()
}
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
case SH2:
EXTCL_CPU_WR_MEM(Waixing_SH2);
EXTCL_SAVE_MAPPER(Waixing_SH2);
EXTCL_AFTER_RD_CHR(Waixing_SH2);
EXTCL_UPDATE_R2006(Waixing_SH2);
EXTCL_WR_CHR(Waixing_SH2);
EXTCL_CPU_EVERY_CYCLE(MMC3);
EXTCL_PPU_000_TO_34X(MMC3);
EXTCL_PPU_000_TO_255(MMC3);
EXTCL_PPU_256_TO_319(MMC3);
EXTCL_PPU_320_TO_34X(MMC3);
mapper.internal_struct[0] = (BYTE *) &waixing;
mapper.internal_struct_size[0] = sizeof(waixing);
mapper.internal_struct[1] = (BYTE *) &mmc3;
mapper.internal_struct_size[1] = sizeof(mmc3);
/* utilizza 0x2000 di CHR RAM extra */
map_chr_ram_extra_init(0x2000);
if (info.reset >= HARD) {
memset(&mmc3, 0x00, sizeof(mmc3));
memset(&irqA12, 0x00, sizeof(irqA12));
memset(&waixing, 0x00, sizeof(waixing));
map_chr_ram_extra_reset();
waixing.reg = 0xFD;
waixing.ctrl[0] = 1;
waixing.ctrl[1] = 1;
map_prg_rom_8k_reset();
map_chr_bank_1k_reset();
waixing.chr_map[0] = 0;
waixing.chr_map[1] = 0;
waixing.chr_map[2] = 0;
waixing.chr_map[4] = 0;
waixing_SH2_PPUFD();
}
irqA12.present = TRUE;
irqA12_delay = 1;
break;
}
void map_init_MMC5(void) {
EXTCL_CPU_WR_MEM(MMC5);
EXTCL_CPU_RD_MEM(MMC5);
EXTCL_SAVE_MAPPER(MMC5);
EXTCL_PPU_256_TO_319(MMC5);
EXTCL_PPU_320_TO_34X(MMC5);
EXTCL_AFTER_RD_CHR(MMC5);
EXTCL_RD_NMT(MMC5);
EXTCL_RD_CHR(MMC5);
EXTCL_LENGTH_CLOCK(MMC5);
EXTCL_ENVELOPE_CLOCK(MMC5);
EXTCL_APU_TICK(MMC5);
mapper.internal_struct[0] = (BYTE *) &mmc5;
mapper.internal_struct_size[0] = sizeof(mmc5);
if (info.reset >= HARD) {
BYTE i;
memset(&mmc5, 0x00, sizeof(mmc5));
memset(&irql2f, 0x00, sizeof(irql2f));
mmc5.prg_mode = MODE3;
mmc5.chr_mode = MODE0;
mmc5.ext_mode = MODE0;
mmc5.chr_last = CHR_S;
mmc5.S3.frequency = 1;
mmc5.S4.frequency = 1;
irql2f.scanline = 255;
irql2f.frame_x = 339;
for (i = 0; i < 4; ++i) {
mmc5.prg_bank[i] = 0xFF;
}
for (i = 0; i < 8; ++i) {
mmc5.chr_s[i] = i;
}
for (i = 0; i < 4; ++i) {
mmc5.chr_b[i] = i;
}
use_chr_s();
} else {
mmc5.S3.length.enabled = 0;
mmc5.S3.length.value = 0;
mmc5.S4.length.enabled = 0;
mmc5.S4.length.value = 0;
}
info.mapper.extend_wr = TRUE;
irql2f.present = TRUE;
switch (info.mapper.submapper) {
case EKROM:
info.prg.ram.banks_8k_plus = 1;
info.prg.ram.bat.banks = 1;
prg_ram_mode = PRG_RAM_8K;
break;
case ELROM:
default:
info.prg.ram.banks_8k_plus = FALSE;
info.prg.ram.bat.banks = FALSE;
prg_ram_mode = PRG_RAM_NONE;
break;
case ETROM:
info.prg.ram.banks_8k_plus = 2;
info.prg.ram.bat.banks = 1;
info.prg.ram.bat.start = 0;
prg_ram_mode = PRG_RAM_16K;
break;
case EWROM:
info.prg.ram.banks_8k_plus = 4;
info.prg.ram.bat.banks = 4;
prg_ram_mode = PRG_RAM_32K;
break;
}
}
