int s6c1372_panel_gpio_init(void)
{
int i, f3_end = 4;
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
}
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
}
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
}
for (i = 0; i < f3_end; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
}
return 0;
}
void exynos4_fimd0_gpio_setup_24bpp(void)
{
unsigned int reg = 0;
#if defined(CONFIG_LCD_WA101S) || defined(CONFIG_LCD_LTE480WV)
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
#elif defined(CONFIG_LCD_AMS369FG06)
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
#elif defined(CONFIG_LCD_LMS501KF03)
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
#endif
/*
* Set DISPLAY_CONTROL register for Display path selection.
*
* DISPLAY_CONTROL[1:0]
* ---------------------
* 00 | MIE
* 01 | MDINE
* 10 | FIMD : selected
* 11 | FIMD
*/
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1 << 1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
#if 1 // TC4
//LVDS_PWDN
err = gpio_request(EXYNOS4_GPL1(0), "GPL1_0");
if (err) {
printk(KERN_ERR "failed to request GPL1 for "
"lcd power control\n");
return ;
}
gpio_direction_output(EXYNOS4_GPL1(0), 1);
s3c_gpio_cfgpin(EXYNOS4_GPL1(0), S3C_GPIO_OUTPUT);
gpio_free(EXYNOS4_GPL1(0));
#endif
}
static void lcd_gpio_cfg(int onoff)
{
if (onoff) {
lcd_gpio_setup(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV2);
lcd_gpio_setup(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV2);
lcd_gpio_setup(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV2);
lcd_gpio_setup(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV2);
}
else {
s3c_gpio_cfgall_range(EXYNOS4_GPF0(0), 8, S3C_GPIO_INPUT, S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgall_range(EXYNOS4_GPF1(0), 8, S3C_GPIO_INPUT, S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgall_range(EXYNOS4_GPF2(0), 8, S3C_GPIO_INPUT, S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgall_range(EXYNOS4_GPF3(0), 4, S3C_GPIO_INPUT, S3C_GPIO_PULL_DOWN);
}
}
void s3cfb_cfg_gpio(struct platform_device *pdev)
{
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 6, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV1);
}
void exynos4_fimd0_gpio_setup_24bpp(void)
{
unsigned int reg;
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV3);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV3);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV3);
exynos4_fimd0_cfg_gpios(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV3);
s5p_gpio_set_drvstr(EXYNOS4_GPF0(0), S5P_GPIO_DRVSTR_LV2);
s5p_gpio_set_drvstr(EXYNOS4_GPF0(1), S5P_GPIO_DRVSTR_LV2);
s5p_gpio_set_drvstr(EXYNOS4_GPF0(2), S5P_GPIO_DRVSTR_LV2);
s5p_gpio_set_drvstr(EXYNOS4_GPF0(3), S5P_GPIO_DRVSTR_LV2);
/*
* Set DISPLAY_CONTROL register for Display path selection.
*
* DISPLAY_CONTROL[1:0]
* ---------------------
* 00 | MIE
* 01 | MDINE
* 10 | FIMD : selected
* 11 | FIMD
*/
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1 << 1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
}
void s3cfb_cfg_gpio(struct platform_device *pdev)
{
int i;
u32 reg;
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPF0(i), S5P_GPIO_DRVSTR_LV4);
}
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPF1(i), S5P_GPIO_DRVSTR_LV4);
}
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPF2(i), S5P_GPIO_DRVSTR_LV4);
}
for (i = 0; i < 4; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPF3(i), S5P_GPIO_DRVSTR_LV4);
}
/* Set FIMD0 bypass */
#ifdef CONFIG_FB_S5P_MDNIE
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg &= ~(1<<13);
reg &= ~(1<<12);
reg &= ~(3<<10);
reg |= (1<<0);
reg &= ~(1<<1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
#else
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1<<1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
#endif
}
static int lcd_cfg_gpio(void)
{
int i, f3_end = 4;
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */
s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE);
}
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE);
}
for (i = 0; i < 8; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE);
}
for (i = 0; i < f3_end; i++) {
s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE);
}
/* MLCD_RST */
s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT);
s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE);
/* LCD_nCS */
s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT);
s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE);
/* LCD_SCLK */
s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT);
s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE);
/* LCD_SDI */
s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT);
s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE);
return 0;
}
void s3cfb_cfg_gpio_sleep(struct platform_device *pdev)
{
int i;
/* Put all LCD pin into "INPUT-PULLDOWN" State to reduce sleep mode current */
for (i = 0; i < 8; i++) {
gpio_direction_input(EXYNOS4_GPF0(i));
s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_DOWN);
}
for (i = 0; i < 8; i++) {
gpio_direction_input(EXYNOS4_GPF1(i));
s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_DOWN);
}
for (i = 0; i < 8; i++) {
gpio_direction_input(EXYNOS4_GPF2(i));
s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_DOWN);
}
for (i = 0; i < 4; i++) {
gpio_direction_input(EXYNOS4_GPF3(i));
s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_DOWN);
}
}
void s3cfb_cfg_gpio(struct platform_device *pdev)
{
int err;
/* add by cym 20150120 */
#if 1
err = gpio_request(EXYNOS4_GPC0(2), "VGA_EN");
if (err) {
printk(KERN_ERR "failed to request VGA_EN\n");
return err;
}
gpio_direction_output(EXYNOS4_GPC0(2), 0);
s3c_gpio_cfgpin(EXYNOS4_GPC0(2), S3C_GPIO_OUTPUT);
gpio_free(EXYNOS4_GPC0(2));
msleep(250);
err = gpio_request(EXYNOS4_GPL0(4), "BK_VDD_EN");
if (err) {
printk(KERN_ERR "failed to request BK_VDD_EN\n");
//return err;
}
gpio_direction_output(EXYNOS4_GPL0(4), 1);
s3c_gpio_cfgpin(EXYNOS4_GPL0(4), S3C_GPIO_OUTPUT);
gpio_free(EXYNOS4_GPL0(4));
printk("(%s, %d): BK_VDD_ON\n", __FUNCTION__, __LINE__);
msleep(100);
#endif
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
s3cfb_gpio_setup_24bpp(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2), S5P_GPIO_DRVSTR_LV4);
#if 1 // TC4
//LVDS_PWDN
err = gpio_request(EXYNOS4_GPL1(0), "GPL1_0");
if (err) {
printk(KERN_ERR "failed to request GPL1 for "
"lcd power control\n");
return err;
}
gpio_direction_output(EXYNOS4_GPL1(0), 1);
s3c_gpio_cfgpin(EXYNOS4_GPL1(0), S3C_GPIO_OUTPUT);
gpio_free(EXYNOS4_GPL1(0));
printk("(%s, %d): LCD_PWDN ON\n", __FUNCTION__, __LINE__);
#endif
}
void exynos4_fimd0_gpio_setup_24bpp(void)
{
unsigned int reg;
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
/*
* Set DISPLAY_CONTROL register for Display path selection.
*
* DISPLAY_CONTROL[1:0]
* ---------------------
* 00 | MIE
* 01 | MDINE
* 10 | FIMD : selected
* 11 | FIMD
*/
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1 << 1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
}
{EXYNOS4_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_D */
{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* MHL_RST */
{EXYNOS4_GPF3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* MHL_INT */
{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
.buck4_voltage[1] = 1100000, /* 1.1V */
.buck4_voltage[2] = 1100000, /* 1.1V */
.buck4_voltage[3] = 1100000, /* 1.1V */
.buck4_voltage[4] = 1100000, /* 1.1V */
.buck4_voltage[5] = 1100000, /* 1.1V */
.buck4_voltage[6] = 1100000, /* 1.1V */
.buck4_voltage[7] = 1100000, /* 1.1V */
.buck_ramp_delay = 25,
.buck_default_idx = 1,
.buck_gpios[0] = EXYNOS4212_GPM3(0),
.buck_gpios[1] = EXYNOS4212_GPM3(1),
.buck_gpios[2] = EXYNOS4212_GPM3(2),
.buck_ds[0] = EXYNOS4_GPF3(1),
.buck_ds[1] = EXYNOS4_GPF3(2),
.buck_ds[2] = EXYNOS4_GPF3(3),
.buck1_init = 1000000,
.buck2_init = 1100000,
.buck3_init = 1000000,
.buck4_init = 1000000,
};
void midas_power_init(void)
{
printk(KERN_INFO "%s\n", __func__);
}
unsigned int get_package_id(void)
{
void __iomem *pkg_reg_addr;
unsigned int pkg_id;
pkg_reg_addr = ioremap(REG_PA_PACKAGE_ID, SZ_4);
pkg_id = readl(pkg_reg_addr);
pkg_id &= (0x3 << 4);
pkg_id >>= 4;
iounmap(pkg_reg_addr);
return pkg_id;
}
static struct gpio hw_rev_gpios[] = {
{ EXYNOS4_GPF3(2), GPIOF_IN, "hw_rev0" },
{ EXYNOS4_GPF3(3), GPIOF_IN, "hw_rev1" },
{ EXYNOS4_GPF2(5), GPIOF_IN, "hw_rev2" },
{ EXYNOS4_GPF2(6), GPIOF_IN, "hw_rev3" },
};
static u32 __init get_hw_rev(void)
{
int ret, i;
u32 hw_rev = 0;
ret = gpio_request_array(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios));
for (i=0; i < ARRAY_SIZE(hw_rev_gpios); i++)
s3c_gpio_setpull(hw_rev_gpios[i].gpio, S3C_GPIO_PULL_NONE);
udelay(9);
{EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
{EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PCM_SEL */
{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SCL*/
{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SDA*/
{EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK2_SEL*/
{EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK3_SEL*/
{EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK4_SEL*/
{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CLK*/
{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CMD*/
{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*eMMC_EN*/
{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(0)*/
{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(1)*/
{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(2)*/
{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(3)*/
{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
},
}, {
.base = (S5P_VA_GPIO1 + 0x1C0),
.eint_offset = 0x38,
.group = 9,
.chip = {
.base = EXYNOS4_GPF2(0),
.ngpio = EXYNOS4_GPIO_F2_NR,
.label = "GPF2",
},
}, {
.base = (S5P_VA_GPIO1 + 0x1E0),
.eint_offset = 0x3C,
.group = 10,
.chip = {
.base = EXYNOS4_GPF3(0),
.ngpio = EXYNOS4_GPIO_F3_NR,
.label = "GPF3",
},
}, {
.base = (S5P_VA_GPIO2 + 0x40),
.eint_offset = 0x8,
.group = 16,
.chip = {
.base = EXYNOS4_GPK0(0),
.ngpio = EXYNOS4_GPIO_K0_NR,
.label = "GPK0",
},
#ifdef CONFIG_MACH_SMDK4X12 // add by rongpin
.pm = &s3c_gpio_pm_nop,
#endif
{EXYNOS4_GPF2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPF3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */
{EXYNOS4_GPL0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SCL_1.8V */
{EXYNOS4_GPL0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE,
S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SDA_1.8V */
#endif
#if defined(CONFIG_QC_MODEM)
{EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
/* GPF1(6) T0 LTE prev level, if not mdm notice it as crash */
{EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
{EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */
{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},
{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},
{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
#if defined(CONFIG_MACH_BAFFIN_KOR_LGT)
{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AUTO_DFS */
{EXYNOS4_GPF2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_RST_1.8V */
#else
{EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
#endif
{EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
#if defined(CONFIG_MACH_SUPERIOR_KOR_SKT)
{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
#else
{EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* KEY_LED_CTRL */
#endif
{EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */
{EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LCD_DET */
{EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */
{EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */
{EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */
{EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_RST */
{EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_INT */
{EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */
{EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */
{EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */
{EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */
{EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */
{EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */
{EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */
{EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */