//*****************************************************************************
//
// The interrupt handler for the Ethernet interrupt.
//
//*****************************************************************************
void
EthernetIntHandler(void)
{
unsigned long ulTemp;
//
// Read and Clear the interrupt.
//
ulTemp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulTemp);
//
// Check to see if an RX Interrupt has occured.
//
if(ulTemp & ETH_INT_RX)
{
//
// Indicate that a packet has been received.
//
HWREGBITW(&g_ulFlags, FLAG_RXPKT) = 1;
//
// Disable Ethernet RX Interrupt.
//
EthernetIntDisable(ETH_BASE, ETH_INT_RX);
}
}
void ethernet_handler(void)
{
unsigned long status;
status = EthernetIntStatus(ETH_BASE, 0);
#ifdef DEBUG
if(status & ETH_INT_RXER)
{
DEBUGOUT("\nEth: Rx err\n\n");
}
if(status & ETH_INT_RXOF)
{
DEBUGOUT("\nEth: Rx overflow\n\n");
}
if(status & ETH_INT_TXER)
{
DEBUGOUT("\nEth: Tx err\n\n");
}
#endif
EthernetIntClear(ETH_BASE, status); //ETH_INT_RX
while(eth_rxput());
return;
}
//*****************************************************************************
//
//! Handles Ethernet interrupts for the lwIP TCP/IP stack.
//!
//! This function handles Ethernet interrupts for the lwIP TCP/IP stack. At
//! the lowest level, all receive packets are placed into a packet queue for
//! processing at a higher level. Also, the transmit packet queue is checked
//! and packets are drained and transmitted through the Ethernet MAC as needed.
//! If the system is configured without an RTOS, additional processing is
//! performed at the interrupt level. The packet queues are processed by the
//! lwIP TCP/IP code, and lwIP periodic timers are serviced (as needed).
//!
//! \return None.
//
//*****************************************************************************
void
lwIPEthernetIntHandler(void)
{
unsigned long ulStatus;
#if !NO_SYS
portBASE_TYPE xWake;
#endif
//
// Read and Clear the interrupt.
//
ulStatus = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulStatus);
//
// The handling of the interrupt is different based on the use of a RTOS.
//
#if NO_SYS
//
// No RTOS is being used. If a transmit/receive interrupt was active,
// run the low-level interrupt handler.
//
if(ulStatus)
{
stellarisif_interrupt(&g_sNetIF);
}
//
// Service the lwIP timers.
//
lwIPServiceTimers();
#else
//
// A RTOS is being used. Signal the Ethernet interrupt task.
//
xQueueSendFromISR(g_pInterrupt, (void *)&ulStatus, &xWake);
//
// Disable the Ethernet interrupts. Since the interrupts have not been
// handled, they are not asserted. Once they are handled by the Ethernet
// interrupt task, it will re-enable the interrupts.
//
EthernetIntDisable(ETH_BASE, ETH_INT_RX | ETH_INT_TX);
//
// Potentially task switch as a result of the above queue write.
//
#if RTOS_SAFERTOS
taskYIELD_FROM_ISR(xWake);
#elif RTOS_FREERTOS
if(xWake == pdTRUE)
{
vPortYieldFromISR();
}
#endif
#endif
}
/**
* In this function, the hardware should be initialized.
* Called from stellarisif_init().
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void
stellarisif_hwinit(struct netif *netif)
{
u32_t temp;
//struct stellarisif *stellarisif = netif->state;
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
#if 1
//
// Enable the Link OK and Link Activity LEDS.
//
GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3);
GPIOPinConfigure(GPIO_PF3_LED0);
GPIOPinConfigure(GPIO_PF2_LED1);
#endif
/* set MAC hardware address */
EthernetMACAddrGet(ETH_BASE, &(netif->hwaddr[0]));
/* maximum transfer unit */
netif->mtu = 1500;
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
/* Do whatever else is needed to initialize interface. */
/* Disable all Ethernet Interrupts. */
EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
temp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, temp);
/* Initialize the Ethernet Controller. */
EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
/*
* Configure the Ethernet Controller for normal operation.
* - Enable TX Duplex Mode
* - Enable TX Padding
* - Enable TX CRC Generation
* - Enable RX Multicast Reception
*/
EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN |ETH_CFG_TX_CRCEN |
ETH_CFG_TX_PADEN | ETH_CFG_RX_AMULEN));
/* Enable the Ethernet Controller transmitter and receiver. */
EthernetEnable(ETH_BASE);
/* Enable the Ethernet Interrupt handler. */
IntEnable(INT_ETH);
/* Enable Ethernet TX and RX Packet Interrupts. */
EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX);
}
/**
* In this function, the hardware should be initialized.
* Called from ethernetif_init().
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void low_level_init(struct netif *netif)
{
u32_t temp;
MAC_Type* mac = (MAC_Type*)netif->state;
//struct ethernetif *ethernetif = netif->state;
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
/* set MAC hardware address */
EthernetMACAddrGet(mac, &(netif->hwaddr[0]));
/* maximum transfer unit */
netif->mtu = 1500;
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP
;//| NETIF_FLAG_LINK_UP;
/* Do whatever else is needed to initialize interface. */
/* Disable all Ethernet Interrupts. */
EthernetIntDisable(
mac,
(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF
| ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
temp = EthernetIntStatus(mac, false);
EthernetIntClear(mac, temp);
/* Initialize the Ethernet Controller. */
EthernetInitExpClk(mac, system_clock_frequency);//SysCtlClockGet());
/*
* Configure the Ethernet Controller for normal operation.
* - Enable TX Duplex Mode
* - Enable TX Padding
* - Enable TX CRC Generation
* - Enable RX Multicast Reception
*/
EthernetConfigSet(
mac,
(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN
| ETH_CFG_RX_AMULEN));
/* Enable the Ethernet Controller transmitter and receiver. */
EthernetEnable(mac);
/* Enable the Ethernet Interrupt handler. */
// IntEnable( INT_ETH);
NVIC_EnableIRQ(Ethernet_IRQn); //THIS IS BAD!
/* Enable Ethernet TX and RX Packet Interrupts. */
EthernetIntEnable(mac, ETH_INT_RX | ETH_INT_TX);
}
/**
* In this function, the hardware should be initialized.
* Called from stellarisif_init().
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void
stellarisif_hwinit(struct netif *netif)
{
u32_t temp;
//struct stellarisif *stellarisif = netif->state;
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
/* set MAC hardware address */
EthernetMACAddrGet(ETH_BASE, &(netif->hwaddr[0]));
/* maximum transfer unit */
netif->mtu = 1500;
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
/* Do whatever else is needed to initialize interface. */
/* Disable all Ethernet Interrupts. */
EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
temp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, temp);
/* Initialize the Ethernet Controller. */
EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
/*
* Configure the Ethernet Controller for normal operation.
* - Enable TX Duplex Mode
* - Enable TX Padding
* - Enable TX CRC Generation
* - Enable RX Multicast Reception
*/
EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN |ETH_CFG_TX_CRCEN |
ETH_CFG_TX_PADEN | ETH_CFG_RX_AMULEN));
/* Enable the Ethernet Controller transmitter and receiver. */
EthernetEnable(ETH_BASE);
IntPrioritySet(INT_ETH, configKERNEL_INTERRUPT_PRIORITY);
/* Enable the Ethernet Interrupt handler. */
IntEnable(INT_ETH);
EthernetPHYWrite(ETH_BASE, PHY_MR17, PHY_MR17_LSCHG_IE);
/* Enable Ethernet TX and RX Packet Interrupts. */
EthernetIntEnable(ETH_BASE, ETH_INT_PHY | ETH_INT_RX | ETH_INT_TX);
}
//*****************************************************************************
//
// Low-Level initialization function for the Ethernet Controller.
//
//*****************************************************************************
void
low_level_init(struct netif *netif)
{
unsigned long ulTemp;
#if ENABLE_ETHERNET_QUEUE_IF
//
// Empty the ethernet frame queue
//
g_ulQueueRead = 0;
g_ulQueueWrite = 0;
#endif
//
// Disable all Ethernet Interrupts.
//
EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
ETH_INT_RX));
ulTemp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulTemp);
//
// Initialize the Ethernet Controller.
//
EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
//
// Configure the Ethernet Controller for normal operation.
// - Enable TX Duplex Mode
// - Enable TX Padding
// - Enable TX CRC Generation
//
EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN |
ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN));
//
// Enable the Ethernet Controller transmitter and receiver.
//
EthernetEnable(ETH_BASE);
//
// Enable the Ethernet Interrupt handler.
//
IntEnable(INT_ETH);
//
// Enable Ethernet TX and RX Packet Interrupts.
//
EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX);
}
//*****************************************************************************
//
// Low-Level initialization function for the Ethernet Controller.
//
//*****************************************************************************
rt_err_t luminaryif_init(rt_device_t dev)
{
unsigned long ulTemp;
//
// Disable all Ethernet Interrupts.
//
EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
ETH_INT_RX));
ulTemp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulTemp);
//
// Initialize the Ethernet Controller.
//
EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
//
// Configure the Ethernet Controller for normal operation.
// - Enable TX Duplex Mode
// - Enable TX Padding
// - Enable TX CRC Generation
// - Enable reception of multicast packets
//
EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN |
ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN | ETH_CFG_RX_AMULEN));
//
// Enable the Ethernet Controller transmitter and receiver.
//
EthernetEnable(ETH_BASE);
//
// Enable the Ethernet Interrupt handler.
//
IntEnable(INT_ETH);
//
// Enable Ethernet TX and RX Packet Interrupts.
//
EthernetIntEnable(ETH_BASE, ETH_INT_RX | ETH_INT_TX);
return RT_EOK;
}
void luminaryif_isr(void)
{
unsigned long ulTemp;
//
// Read and Clear the interrupt.
//
ulTemp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulTemp);
//
// Check to see if an RX Interrupt has occured.
//
if(ulTemp & ETH_INT_RX)
{
//
// Indicate that a packet has been received.
//
rt_err_t result;
/* a frame has been received */
result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent));
if(result != RT_EOK) rt_set_errno(-RT_ERROR);
//
// Disable Ethernet RX Interrupt.
//
EthernetIntDisable(ETH_BASE, ETH_INT_RX);
}
if(ulTemp & ETH_INT_TX)
{
/* A frame has been transmitted. */
rt_sem_release(&tx_sem);
}
}
//*****************************************************************************
//
// This example demonstrates the use of the Ethernet Controller with the uIP
// TCP/IP stack.
//
//*****************************************************************************
int
main(void)
{
uip_ipaddr_t ipaddr;
static struct uip_eth_addr sTempAddr;
long lPeriodicTimer, lARPTimer, lPacketLength;
unsigned long ulUser0, ulUser1;
unsigned long ulTemp;
//
// Set the clocking to run directly from the crystal.
//
SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_8MHZ);
//
// Initialize the OLED display.
//
RIT128x96x4Init(1000000);
RIT128x96x4StringDraw("Ethernet with uIP", 12, 0, 15);
//
// Enable and Reset the Ethernet Controller.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH);
SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);
//
// Enable Port F for Ethernet LEDs.
// LED0 Bit 3 Output
// LED1 Bit 2 Output
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3);
//
// Configure SysTick for a periodic interrupt.
//
SysTickPeriodSet(SysCtlClockGet() / SYSTICKHZ);
SysTickEnable();
SysTickIntEnable();
//
// Intialize the Ethernet Controller and disable all Ethernet Controller
// interrupt sources.
//
EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
ulTemp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulTemp);
//
// Initialize the Ethernet Controller for operation.
//
EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
//
// Configure the Ethernet Controller for normal operation.
// - Full Duplex
// - TX CRC Auto Generation
// - TX Padding Enabled
//
EthernetConfigSet(ETH_BASE, (ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
ETH_CFG_TX_PADEN));
//
// Wait for the link to become active.
//
RIT128x96x4StringDraw("Waiting for Link", 12, 8, 15);
ulTemp = EthernetPHYRead(ETH_BASE, PHY_MR1);
while((ulTemp & 0x0004) == 0)
{
ulTemp = EthernetPHYRead(ETH_BASE, PHY_MR1);
}
RIT128x96x4StringDraw("Link Established", 12, 16, 15);
//
// Enable the Ethernet Controller.
//
EthernetEnable(ETH_BASE);
//
// Enable the Ethernet interrupt.
//
IntEnable(INT_ETH);
//
// Enable the Ethernet RX Packet interrupt source.
//
EthernetIntEnable(ETH_BASE, ETH_INT_RX);
//
// Enable all processor interrupts.
//
IntMasterEnable();
//
// Initialize the uIP TCP/IP stack.
//
uip_init();
#ifdef USE_STATIC_IP
uip_ipaddr(ipaddr, DEFAULT_IPADDR0, DEFAULT_IPADDR1, DEFAULT_IPADDR2,
DEFAULT_IPADDR3);
uip_sethostaddr(ipaddr);
DisplayIPAddress(ipaddr, 18, 24);
uip_ipaddr(ipaddr, DEFAULT_NETMASK0, DEFAULT_NETMASK1, DEFAULT_NETMASK2,
DEFAULT_NETMASK3);
uip_setnetmask(ipaddr);
#else
uip_ipaddr(ipaddr, 0, 0, 0, 0);
uip_sethostaddr(ipaddr);
DisplayIPAddress(ipaddr, 18, 24);
uip_ipaddr(ipaddr, 0, 0, 0, 0);
uip_setnetmask(ipaddr);
#endif
//
// Configure the hardware MAC address for Ethernet Controller filtering of
// incoming packets.
//
// For the Ethernet Eval Kits, the MAC address will be stored in the
// non-volatile USER0 and USER1 registers. These registers can be read
// using the FlashUserGet function, as illustrated below.
//
FlashUserGet(&ulUser0, &ulUser1);
if((ulUser0 == 0xffffffff) || (ulUser1 == 0xffffffff))
{
//
// We should never get here. This is an error if the MAC address has
// not been programmed into the device. Exit the program.
//
RIT128x96x4StringDraw("MAC Address", 0, 16, 15);
RIT128x96x4StringDraw("Not Programmed!", 0, 24, 15);
while(1)
{
}
}
//
// Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
// address needed to program the hardware registers, then program the MAC
// address into the Ethernet Controller registers.
//
sTempAddr.addr[0] = ((ulUser0 >> 0) & 0xff);
sTempAddr.addr[1] = ((ulUser0 >> 8) & 0xff);
sTempAddr.addr[2] = ((ulUser0 >> 16) & 0xff);
sTempAddr.addr[3] = ((ulUser1 >> 0) & 0xff);
sTempAddr.addr[4] = ((ulUser1 >> 8) & 0xff);
sTempAddr.addr[5] = ((ulUser1 >> 16) & 0xff);
//
// Program the hardware with it's MAC address (for filtering).
//
EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
uip_setethaddr(sTempAddr);
//
// Initialize the TCP/IP Application (e.g. web server).
//
httpd_init();
#ifndef USE_STATIC_IP
//
// Initialize the DHCP Client Application.
//
dhcpc_init(&sTempAddr.addr[0], 6);
dhcpc_request();
#endif
//
// Main Application Loop.
//
lPeriodicTimer = 0;
lARPTimer = 0;
while(true)
{
//
// Wait for an event to occur. This can be either a System Tick event,
// or an RX Packet event.
//
while(!g_ulFlags)
{
}
//
// If SysTick, Clear the SysTick interrupt flag and increment the
// timers.
//
if(HWREGBITW(&g_ulFlags, FLAG_SYSTICK) == 1)
{
HWREGBITW(&g_ulFlags, FLAG_SYSTICK) = 0;
lPeriodicTimer += SYSTICKMS;
lARPTimer += SYSTICKMS;
}
//
// Check for an RX Packet and read it.
//
lPacketLength = EthernetPacketGetNonBlocking(ETH_BASE, uip_buf,
sizeof(uip_buf));
if(lPacketLength > 0)
{
//
// Set uip_len for uIP stack usage.
//
uip_len = (unsigned short)lPacketLength;
//
// Clear the RX Packet event and renable RX Packet interrupts.
//
if(HWREGBITW(&g_ulFlags, FLAG_RXPKT) == 1)
{
HWREGBITW(&g_ulFlags, FLAG_RXPKT) = 0;
EthernetIntEnable(ETH_BASE, ETH_INT_RX);
}
//
// Process incoming IP packets here.
//
if(BUF->type == htons(UIP_ETHTYPE_IP))
{
uip_arp_ipin();
uip_input();
//
// If the above function invocation resulted in data that
// should be sent out on the network, the global variable
// uip_len is set to a value > 0.
//
if(uip_len > 0)
{
uip_arp_out();
EthernetPacketPut(ETH_BASE, uip_buf, uip_len);
uip_len = 0;
}
}
//
// Process incoming ARP packets here.
//
else if(BUF->type == htons(UIP_ETHTYPE_ARP))
{
uip_arp_arpin();
//
// If the above function invocation resulted in data that
// should be sent out on the network, the global variable
// uip_len is set to a value > 0.
//
if(uip_len > 0)
{
EthernetPacketPut(ETH_BASE, uip_buf, uip_len);
uip_len = 0;
}
}
}
//
// Process TCP/IP Periodic Timer here.
//
if(lPeriodicTimer > UIP_PERIODIC_TIMER_MS)
{
lPeriodicTimer = 0;
for(ulTemp = 0; ulTemp < UIP_CONNS; ulTemp++)
{
uip_periodic(ulTemp);
//
// If the above function invocation resulted in data that
// should be sent out on the network, the global variable
// uip_len is set to a value > 0.
//
if(uip_len > 0)
{
uip_arp_out();
EthernetPacketPut(ETH_BASE, uip_buf, uip_len);
uip_len = 0;
}
}
#if UIP_UDP
for(ulTemp = 0; ulTemp < UIP_UDP_CONNS; ulTemp++)
{
uip_udp_periodic(ulTemp);
//
// If the above function invocation resulted in data that
// should be sent out on the network, the global variable
// uip_len is set to a value > 0.
//
if(uip_len > 0)
{
uip_arp_out();
EthernetPacketPut(ETH_BASE, uip_buf, uip_len);
uip_len = 0;
}
}
#endif // UIP_UDP
}
//
// Process ARP Timer here.
//
if(lARPTimer > UIP_ARP_TIMER_MS)
{
lARPTimer = 0;
uip_arp_timer();
}
}
}
