Ejemplo n.º 1
0
/* transaction time: .6 to 1 ms typically */
int lgw_spi_w(void *spi_target, uint8_t address, uint8_t data) {
	struct mpsse_context *mpsse = spi_target;
	uint8_t out_buf[2];
	int a, b, c;
	
	/* check input variables */
	CHECK_NULL(spi_target);
	if ((address & 0x80) != 0) {
		DEBUG_MSG("WARNING: SPI address > 127\n");
	}
	
	/* prepare frame to be sent */
	out_buf[0] = WRITE_ACCESS | (address & 0x7F);
	out_buf[1] = data;
	
	/* MPSSE transaction */
	a = Start(mpsse);
	b = FastWrite(mpsse, (char *)out_buf, 2);
	c = Stop(mpsse);
	
	/* determine return code */
	if ((a != MPSSE_OK) || (b != MPSSE_OK) || (c != MPSSE_OK)) {
		DEBUG_MSG("ERROR: SPI WRITE FAILURE\n");
		return LGW_SPI_ERROR;
	} else {
		DEBUG_MSG("Note: SPI write success\n");
		return LGW_SPI_SUCCESS;
	}
}
Ejemplo n.º 2
0
void VDFileAsync9x::FastWriteEnd() {
	FastWrite(NULL, mSectorSize - 1);

	mState = kStateFlush;
	mWriteOccurred.signal();
	ThreadWait();

	if (mpError)
		ThrowError();
}
Ejemplo n.º 3
0
void VDFileAsyncNT::FastWriteEnd() {
	if (mhFileFast != INVALID_HANDLE_VALUE) {
		FastWrite(NULL, mSectorSize - 1);
		mState = kStateFlush;
		mWriteOccurred.signal();
		ThreadWait();
	}

	if (mpError)
		ThrowError();
}
Ejemplo n.º 4
0
void VDFileAsync9x::SafeTruncateAndClose(sint64 pos) {
	if (mhFileSlow != INVALID_HANDLE_VALUE) {
		FastWrite(NULL, mSectorSize - 1);

		mState = kStateFlush;
		mWriteOccurred.signal();
		ThreadWait();

		Extend(pos);
		Close();
	}
}
Ejemplo n.º 5
0
/* transaction time: 2ms for 16 data bytes @6MHz, 1kB chunks */
int lgw_spi_rb(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, uint8_t address, uint8_t *data, uint16_t size) {
	struct mpsse_context *mpsse = spi_target;
	uint8_t command[2];
    uint8_t command_size;
	int size_to_do, chunk_size, offset;
	int a=0, b=0, c=0, d=0;
	int i;
	
	/* check input parameters */
	CHECK_NULL(spi_target);
	if ((address & 0x80) != 0) {
		DEBUG_MSG("WARNING: SPI address > 127\n");
	}
	CHECK_NULL(data);
	if (size == 0) {
		DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n");
		return LGW_SPI_ERROR;
	}
	
	/* prepare command bytes */
    if (spi_mux_mode == LGW_SPI_MUX_MODE1) {
        command[0] = spi_mux_target;
        command[1] = READ_ACCESS | (address & 0x7F);
        command_size = 2;
    } else {
        command[0] = READ_ACCESS | (address & 0x7F);
        command_size = 1;
    }
	size_to_do = size;
	
	/* start MPSSE transaction */
	a = Start(mpsse);
	b = FastWrite(mpsse, (char *)&command, command_size);
	for (i=0; size_to_do > 0; ++i) {
		chunk_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK;
		offset = i * LGW_BURST_CHUNK;
		c = FastRead(mpsse, (char *)(data + offset), chunk_size);
		size_to_do -= chunk_size; /* subtract the quantity of data already transferred */
	}
	d = Stop(mpsse);
	
	/* determine return code (only the last FastRead is checked) */
	if ((a != MPSSE_OK) || (b != MPSSE_OK) || (c != MPSSE_OK) || (d != MPSSE_OK)) {
		DEBUG_MSG("ERROR: SPI BURST READ FAILURE\n");
		return LGW_SPI_ERROR;
	} else {
		DEBUG_MSG("Note: SPI burst read success\n");
		return LGW_SPI_SUCCESS;
	}
}
Ejemplo n.º 6
0
 void ByteBuffer::FastWrite( T const( &a )[ len ] )
 {
     if( std::is_pod<T>::value )
     {
         FastWrite( (char*)a, len * sizeof( T ) );
     }
     else
     {
         for( int i = 0; i < len; ++i )
         {
             FastWriteSwitch( *this, a[ i ] );
         }
     }
 }
Ejemplo n.º 7
0
 void ByteBuffer::Write( T const( &a )[ len ] )
 {
     if( std::is_pod<T>::value )
     {
         auto siz = len * ( int )sizeof( T );
         Reserve( dataLen + siz );
         FastWrite( (char*)a, len * sizeof( T ) );
     }
     else
     {
         for( int i = 0; i < len; ++i )
         {
             Write( a[ i ] );
         }
     }
 }
Ejemplo n.º 8
0
/* transaction time: 0.5ms for 16 data bytes @6MHz, 1kB chunks */
int lgw_spi_wb(void *spi_target, uint8_t address, uint8_t *data, uint16_t size) {
	struct mpsse_context *mpsse = spi_target;
	uint8_t command;
	uint8_t *out_buf = NULL;
	int size_to_do, buf_size, chunk_size, offset;
	int a=0, b=0, c=0;
	int i;
	
	/* check input parameters */
	CHECK_NULL(spi_target);
	if ((address & 0x80) != 0) {
		DEBUG_MSG("WARNING: SPI address > 127\n");
	}
	CHECK_NULL(data);
	if (size == 0) {
		DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n");
		return LGW_SPI_ERROR;
	}
	
	/* prepare command byte */
	command = WRITE_ACCESS | (address & 0x7F);
	size_to_do = size + 1; /* add a byte for the address */
	
	/* allocate data buffer */
	buf_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK;
	out_buf = malloc(buf_size);
	if (out_buf == NULL) {
		DEBUG_MSG("ERROR: MALLOC FAIL\n");
		return LGW_SPI_ERROR;
	}
	
	/* start MPSSE transaction */
	a = Start(mpsse);
	for (i=0; size_to_do > 0; ++i) {
		chunk_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK;
		if (i == 0) {
			/* first chunk, need to append the address */
			out_buf[0] = command;
			memcpy(out_buf+1, data, chunk_size-1);
		} else {
			/* following chunks, just copy the data */
			offset = (i * LGW_BURST_CHUNK) - 1;
			memcpy(out_buf, data + offset, chunk_size);
		}
		b = FastWrite(mpsse, (char *)out_buf, chunk_size);
		size_to_do -= chunk_size; /* subtract the quantity of data already transferred */
	}
	c = Stop(mpsse);
	
	/* deallocate data buffer */
	free(out_buf);
	
	/* determine return code (only the last FastWrite is checked) */
	if ((a != MPSSE_OK) || (b != MPSSE_OK) || (c != MPSSE_OK)) {
		DEBUG_MSG("ERROR: SPI BURST WRITE FAILURE\n");
		return LGW_SPI_ERROR;
	} else {
		DEBUG_MSG("Note: SPI burst write success\n");
		return LGW_SPI_SUCCESS;
	}
}
Ejemplo n.º 9
0
 void ByteBuffer::FastWrite( char const( &s )[ len ] )
 {
     FastVarWrite( uint(len - 1) );
     FastWrite( s, len - 1 );
 }
Ejemplo n.º 10
0
 void ByteBuffer::FastWriteMultiCore( T const& v, TS const& ...vs )
 {
     FastWrite( v );
     FastWriteMultiCore( vs... );
 }
Ejemplo n.º 11
0
 void ByteBuffer::FastWriteMultiCore( T const& v )
 {
     FastWrite( v );
 }