static int RalinkGdmaInit(void)
{
uint32_t Ret=0;
uint32_t val = 0;
printk("Enable Ralink GDMA Controller Module \n");
#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
printk("GDMA IP Version=%d\n", GET_GDMA_IP_VER);
#endif
Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
IRQF_DISABLED, "Ralink_DMA", NULL);
if(Ret){
GDMA_PRINT("IRQ %d is not free.\n", SURFBOARDINT_DMA);
return 1;
}
//Enable GDMA interrupt
val = le32_to_cpu(*(volatile u32 *)(RALINK_REG_INTENA));
val |= RALINK_INTCTL_DMA;
GDMA_WRITE_REG(RALINK_REG_INTENA, val);
//Channel0~Channel7 are round-robin
#if defined (CONFIG_RALINK_RT3052)
GDMA_WRITE_REG(RALINK_GDMAGCT, 0x01);
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
GDMA_WRITE_REG(RALINK_GDMA_GCT, 0x01);
#else
#error Please Choose System Type
#endif
return 0;
}
int _nand_dma_sync(void)
{
//unmask to start dma
unsigned long data;
int retry = 1000000; //fixme
data = GDMA_READ_REG(GDMA_CTRL_REG1(DMA_CHNUM));
data &= ~( 0x01 << CH_MASK_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG1(DMA_CHNUM), data);
#if defined (CONFIG_RALINK_RT3052)
// sync status
while(!(GDMA_READ_REG(RALINK_GDMAISTS) & (1<<DMA_CHNUM)) && retry--) {
ndelay(1);
// do nothing
}
if (!(GDMA_READ_REG(RALINK_GDMAISTS) & (1<<DMA_CHNUM))) {
return -1;
}
GDMA_WRITE_REG(RALINK_GDMAISTS, 1<<DMA_CHNUM);
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
while(!(GDMA_READ_REG(RALINK_GDMA_DONEINT) & (1<<DMA_CHNUM)) && retry--) {
ndelay(1);
}
if (!(GDMA_READ_REG(RALINK_GDMA_DONEINT) & (1<<DMA_CHNUM))) {
return -1;
}
GDMA_WRITE_REG(RALINK_GDMA_DONEINT, 1<<DMA_CHNUM);
#endif
return 0;
}
int _set_gdma_ch(unsigned long dst,
unsigned long src, unsigned int len, int burst_size,
int soft_mode, int src_req_type, int dst_req_type,
int src_burst_mode, int dst_burst_mode)
{
unsigned long data;
//src
GDMA_WRITE_REG(GDMA_SRC_REG(DMA_CHNUM), (src & 0x1fffffff));
//dst
GDMA_WRITE_REG(GDMA_DST_REG(DMA_CHNUM), (dst & 0x1fffffff));
//control 1,
data = 0;
// data = (0 << CH_UNMASK_INTEBL_OFFSET);
data |= ( DMA_CHNUM << NEXT_UNMASK_CH_OFFSET);
data |= ( (soft_mode == 0) << CH_MASK_OFFSET);
#if 0
#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352)
data |= (src_req_type << SRC_DMA_REQ_OFFSET);
data |= (dst_req_type << DST_DMA_REQ_OFFSET);
#endif
#endif
// frank added
data |= (src_req_type << SRC_DMA_REQ_OFFSET);
data |= (dst_req_type << DST_DMA_REQ_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG1(DMA_CHNUM), data);
// control
data = (len << TRANS_CNT_OFFSET);
#if 0
#ifdef CONFIG_RALINK_RT3052
data |= (src_req_type << SRC_DMA_REQ_OFFSET);
data |= (dst_req_type << DST_DMA_REQ_OFFSET);
#endif
#endif
data |= (src_burst_mode << SRC_BRST_MODE_OFFSET);
data |= (dst_burst_mode << DST_BRST_MODE_OFFSET);
data |= (burst_size << BRST_SIZE_OFFSET);
// data |= (0 << INT_EBL_OFFSET);
data |= ((soft_mode != 0) << MODE_SEL_OFFSET);
data |= (0x01<<CH_EBL_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG(DMA_CHNUM), data);
return 1;
}
/**
* @brief GDMA interrupt handler
*
* When GDMA transcation is done, call related handler
* to do the remain job.
*
*/
irqreturn_t GdmaIrqHandler(
int irq,
void *irqaction
)
{
u32 Ch=0;
u32 flags;
u32 GdmaStatus=GDMA_READ_REG(RALINK_GDMAISTS);
GDMA_PRINT("Rcv Gdma Interrupt=%x\n",GdmaStatus);
spin_lock_irqsave(&gdma_int_lock, flags);
//UnMask error
for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
if(GdmaStatus & (0x1 << (Ch+UMASK_INT_STATUS_OFFSET)) ) {
if(GdmaUnMaskIntCallback[Ch] != NULL) {
//write 1 clear
GDMA_WRITE_REG(RALINK_GDMAISTS,
1<< (Ch + UMASK_INT_STATUS_OFFSET));
GdmaUnMaskIntCallback[Ch](Ch);
}
}
}
//processing done
for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
if(GdmaStatus & (0x1<<Ch)) {
if(GdmaTxDoneCallback[Ch] != NULL) {
//write 1 clear
GDMA_WRITE_REG(RALINK_GDMAISTS,
1<< (Ch + TX_DONE_INT_STATUS_OFFSET));
GdmaTxDoneCallback[Ch](Ch);
}
}
}
spin_unlock_irqrestore(&gdma_int_lock, flags);
return IRQ_HANDLED;
}
/**
* @brief Insert new GDMA entry to start GDMA transaction
*
* @param ChNum GDMA channel number
* @retval 1 success
* @retval 0 fail
*/
int GdmaReqQuickIns(uint32_t ChNum)
{
uint32_t Data=0;
//Mask Channel
Data = GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
Data |= ( 0x1 << CH_MASK_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
//Channel Enable
Data = GDMA_READ_REG(GDMA_CTRL_REG(ChNum));
Data |= (0x01<<CH_EBL_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG(ChNum), Data);
return 1;
}
void _release_dma_buf(void)
{
unsigned long data;
data = GDMA_READ_REG(GDMA_CTRL_REG(DMA_CHNUM));
data &= ~( 0x01 << CH_EBL_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG(DMA_CHNUM), data);
}
static void __exit RalinkGdmaExit(void)
{
printk("Disable Ralink GDMA Controller Module\n");
//Disable GDMA interrupt
GDMA_WRITE_REG(RALINK_REG_INTDIS, RALINK_INTCTL_DMA);
free_irq(SURFBOARDINT_DMA, NULL);
}
/**
* @brief Set channel is unmasked
*
* You can unmask the channel to start GDMA transaction.
*
* When GDMA controller comes back from another channel (chain feature)
*
* >> Channel Mask=0: It's strange, and turns on related bit in GDMA interrupt
* status register (16:23 Unmasked)
*
* >> Channel Mask=1: It'll start GDMA transation, and clear this bit.
*
* @param ChNum GDMA channel number
* @retval 1 success
* @retval 0 fail
*/
int GdmaUnMaskChannel(uint32_t ChNum)
{
uint32_t Data=0;
Data=GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
Data &= ~( 0x01 << CH_MASK_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
GDMA_PRINT("%s: Write %0X to %X\n", __FUNCTION__, Data, GDMA_CTRL_REG1(ChNum));
return 1;
}
static int RalinkGdmaInit(void)
{
uint32_t Ret=0;
GDMA_PRINT("Enable Ralink GDMA Controller Module\n");
Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
SA_INTERRUPT, "Ralink_DMA", NULL);
if(Ret){
GDMA_PRINT("IRQ %d is not free.\n", SURFBOARDINT_DMA);
return 1;
}
//Enable GDMA interrupt
GDMA_WRITE_REG(RALINK_REG_INTENA, RALINK_INTCTL_DMA);
//Channel0~Channel7 are round-robin
GDMA_WRITE_REG(RALINK_GDMAGCT, 0x01);
return 0;
}
/**
* @brief GDMA interrupt handler
*
* When GDMA transcation is done, call related handler
* to do the remain job.
*
*/
irqreturn_t GdmaIrqHandler(
int irq,
void *irqaction
)
{
u32 Ch=0;
unsigned long flags;
#if defined (CONFIG_RALINK_RT3052)
u32 GdmaUnMaskStatus=GDMA_READ_REG(RALINK_GDMAISTS) & 0xFF0000;
u32 GdmaDoneStatus=GDMA_READ_REG(RALINK_GDMAISTS) & 0xFF;
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
u32 GdmaUnMaskStatus=GDMA_READ_REG(RALINK_GDMA_UNMASKINT);
u32 GdmaDoneStatus=GDMA_READ_REG(RALINK_GDMA_DONEINT);
#endif
//GDMA_PRINT("========================================\n");
//GDMA_PRINT("GdmaUnMask Interrupt=%x\n",GdmaUnMaskStatus);
//GDMA_PRINT("GdmaDone Interrupt=%x\n",GdmaDoneStatus);
//GDMA_PRINT("========================================\n");
spin_lock_irqsave(&gdma_int_lock, flags);
//UnMask error
for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
if(GdmaUnMaskStatus & (0x1 << (UNMASK_INT_STATUS(Ch))) ) {
if(GdmaUnMaskIntCallback[Ch] != NULL) {
GdmaUnMaskIntCallback[Ch](Ch);
}
}
}
//write 1 clear
#if defined (CONFIG_RALINK_RT3052)
GDMA_WRITE_REG(RALINK_GDMAISTS, GdmaUnMaskStatus);
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
GDMA_WRITE_REG(RALINK_GDMA_UNMASKINT, GdmaUnMaskStatus);
#endif
//processing done
for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
if(GdmaDoneStatus & (0x1<<Ch)) {
if(GdmaDoneIntCallback[Ch] != NULL) {
GdmaDoneIntCallback[Ch](Ch);
}
}
}
//write 1 clear
#if defined (CONFIG_RALINK_RT3052)
GDMA_WRITE_REG(RALINK_GDMAISTS, GdmaDoneStatus);
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
GDMA_WRITE_REG(RALINK_GDMA_DONEINT, GdmaDoneStatus);
#endif
spin_unlock_irqrestore(&gdma_int_lock, flags);
return IRQ_HANDLED;
}
int _GdmaReqEntryIns(GdmaReqEntry *NewEntry)
{
uint32_t Data=0;
GDMA_PRINT("== << GDMA Control Reg (Channel=%d) >> ===\n", NewEntry->ChNum);
GDMA_PRINT(" Channel Source Addr = %x \n", NewEntry->Src);
GDMA_PRINT(" Channel Dest Addr = %x \n", NewEntry->Dst);
GDMA_PRINT(" Transfer Count=%d\n", NewEntry->TransCount);
GDMA_PRINT(" Source DMA Req= DMA_REQ%d\n", NewEntry->SrcReqNum);
GDMA_PRINT(" Dest DMA Req= DMA_REQ%d\n", NewEntry->DstReqNum);
GDMA_PRINT(" Source Burst Mode=%s\n", NewEntry->SrcBurstMode ? "Fix" : "Inc");
GDMA_PRINT(" Dest Burst Mode=%s\n", NewEntry->DstBurstMode ? "Fix" : "Inc");
GDMA_PRINT(" Burst Size=%s\n", NewEntry->BurstSize ==0 ? "1 transfer" : \
NewEntry->BurstSize ==1 ? "2 transfer" :\
NewEntry->BurstSize ==2 ? "4 transfer" :\
NewEntry->BurstSize ==3 ? "8 transfer" :\
NewEntry->BurstSize ==4 ? "16 transfer" :\
"Error");
GDMA_PRINT(" Hardware/Software Mode = %s\n", NewEntry->SoftMode ?
"Soft" : "Hw");
GDMA_PRINT("== << GDMA Control Reg1 (Channel=%d) >> =\n", NewEntry->ChNum);
GDMA_PRINT("Channel Done Interrput=%s\n", (NewEntry->DoneIntCallback!=NULL) ?
"Enable" : "Disable");
GDMA_PRINT("Channel Unmasked Int=%s\n", (NewEntry->UnMaskIntCallback!=NULL) ?
"Enable" : "Disable");
#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3883)
GDMA_PRINT("Coherent Interrupt =%s\n", (NewEntry->CoherentIntEbl==1)?
"Enable" : "Disable");
#endif
GDMA_PRINT("Next Unmasked Channel=%d\n", NewEntry->NextUnMaskCh);
GDMA_PRINT("Channel Mask=%d\n", NewEntry->ChMask);
GDMA_PRINT("========================================\n");
GDMA_WRITE_REG(GDMA_SRC_REG(NewEntry->ChNum), NewEntry->Src);
GDMA_PRINT("SrcAddr: Write %0X to %X\n", \
NewEntry->Src, GDMA_SRC_REG(NewEntry->ChNum));
GDMA_WRITE_REG(GDMA_DST_REG(NewEntry->ChNum), NewEntry->Dst);
GDMA_PRINT("DstAddr: Write %0X to %X\n", \
NewEntry->Dst, GDMA_DST_REG(NewEntry->ChNum));
Data |= ( (NewEntry->NextUnMaskCh) << NEXT_UNMASK_CH_OFFSET);
Data |= ( NewEntry->ChMask << CH_MASK_OFFSET);
#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3883)
Data |= ( NewEntry->CoherentIntEbl << COHERENT_INT_EBL_OFFSET);
#endif
if(NewEntry->UnMaskIntCallback!=NULL) {
Data |= (0x01<<CH_UNMASKINT_EBL_OFFSET);
GdmaUnMaskIntCallback[NewEntry->ChNum] = NewEntry->UnMaskIntCallback;
}
#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
Data |= (NewEntry->SrcReqNum << SRC_DMA_REQ_OFFSET);
Data |= (NewEntry->DstReqNum << DST_DMA_REQ_OFFSET);
#endif
GDMA_WRITE_REG(GDMA_CTRL_REG1(NewEntry->ChNum), Data);
GDMA_PRINT("CTRL1: Write %08X to %8X\n", Data, GDMA_CTRL_REG1(NewEntry->ChNum));
Data = ((NewEntry->TransCount) << TRANS_CNT_OFFSET);
#if defined (CONFIG_RALINK_RT3052)
Data |= (NewEntry->SrcReqNum << SRC_DMA_REQ_OFFSET);
Data |= (NewEntry->DstReqNum << DST_DMA_REQ_OFFSET);
#endif
Data |= (NewEntry->SrcBurstMode << SRC_BRST_MODE_OFFSET);
Data |= (NewEntry->DstBurstMode << DST_BRST_MODE_OFFSET);
Data |= (NewEntry->BurstSize << BRST_SIZE_OFFSET);
if(NewEntry->DoneIntCallback!=NULL) {
Data |= (0x01<<CH_DONEINT_EBL_OFFSET);
GdmaDoneIntCallback[NewEntry->ChNum] = NewEntry->DoneIntCallback;
}
if(NewEntry->SoftMode) {
Data |= (0x01<<MODE_SEL_OFFSET);
}
Data |= (0x01<<CH_EBL_OFFSET);
GDMA_WRITE_REG(GDMA_CTRL_REG(NewEntry->ChNum), Data);
GDMA_PRINT("CTRL: Write %08X to %8X\n", Data, GDMA_CTRL_REG(NewEntry->ChNum));
//if there is no interrupt handler, this function will
//return 1 until GDMA done.
if(NewEntry->DoneIntCallback==NULL) {
//wait for GDMA processing done
#if defined (CONFIG_RALINK_RT3052)
while((GDMA_READ_REG(RALINK_GDMAISTS) &
(0x1<<NewEntry->ChNum))==0);
//write 1 clear
GDMA_WRITE_REG(RALINK_GDMAISTS, 1<< NewEntry->ChNum);
#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
while((GDMA_READ_REG(RALINK_GDMA_DONEINT) &
(0x1<<NewEntry->ChNum))==0);
//write 1 clear
GDMA_WRITE_REG(RALINK_GDMA_DONEINT, 1<< NewEntry->ChNum);
#endif
}
return 1;
}
