static SEM_PC
SEM_FN_NAME (lm32bf,lhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
CPU (h_gr[FLD (f_r1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
return vpc;
#undef FLD
}
HI
frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
USI hsr0;
FRV_CACHE *cache;
/* Check for access exceptions. */
address = check_data_read_address (current_cpu, address, 1);
address = check_readwrite_address (current_cpu, address, 1);
/* If we need to count cycles, then the cache operation will be
initiated from the model profiling functions.
See frvbf_model_.... */
hsr0 = GET_HSR0 ();
cache = CPU_DATA_CACHE (current_cpu);
if (model_insn)
{
CPU_LOAD_ADDRESS (current_cpu) = address;
CPU_LOAD_LENGTH (current_cpu) = 2;
CPU_LOAD_SIGNED (current_cpu) = 1;
return 0xb711; /* any random value */
}
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
return read_mem_unaligned_HI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, HI, 2);
}
return GETMEMHI (current_cpu, pc, address);
}
