/**
* \brief This function configures the direction of a pin as input or
* output.
*
* \param baseAdd The memory address of the GPIO instance being used.
* \param pinNumber The serial number of the GPIO pin.
* The 144 GPIO pins have serial numbers from 1 to 144.
*
* \param pinDir The direction to be set for the pin.
* This can take the values:
* 1> GPIO_DIR_INPUT, for configuring the pin as input.
* 2> GPIO_DIR_OUTPUT, for configuring the pin as output.
*
* \return None.
*
* \note Here we write to the DIRn register. Writing a logic 1 configures
* the pin as input and writing logic 0 as output. By default, all
* the pins are set as input pins.
*/
void GPIODirModeSet(unsigned int baseAdd, unsigned int pinNumber,
unsigned int pinDir)
{
unsigned int regNumber = 0;
unsigned int pinOffset = 0;
/*
** Each register contains settings for each pin of two banks. The 32 bits
** represent 16 pins each from the banks. Thus the register number must be
** calculated based on 32 pins boundary.
*/
regNumber = (pinNumber - 1)/32;
/*
** In every register the least significant bits starts with a GPIO number on
** a boundary of 32. Thus the pin offset must be calculated based on 32
** pins boundary. Ex: 'pinNumber' of 1 corresponds to bit 0 in
** 'register_name01'.
*/
pinOffset = (pinNumber - 1) % 32;
if(GPIO_DIR_OUTPUT == pinDir)
{
HWREG(baseAdd + GPIO_DIR(regNumber)) &= ~(1 << pinOffset);
}
else
{
HWREG(baseAdd + GPIO_DIR(regNumber)) |= (1 << pinOffset);
}
}
static int qrd_gpios_request_enable(const struct msm_gpio *table, int size)
{
int i;
const struct msm_gpio *g;
struct gpiomux_setting setting;
int rc = msm_gpios_request(table, size);
if (!rc){
for (i = 0; i < size; i++) {
g = table + i;
/* use msm_gpiomux_write which can save old configuration */
setting.func = GPIO_FUNC(g->gpio_cfg);
setting.dir = GPIO_DIR(g->gpio_cfg);
setting.pull = GPIO_PULL(g->gpio_cfg);
setting.drv = GPIO_DRVSTR(g->gpio_cfg);
msm_gpiomux_write(GPIO_PIN(g->gpio_cfg), GPIOMUX_ACTIVE, &setting, NULL);
pr_debug("I2C pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
}
}
return rc;
}
/*
* GPIO setup:
* Enable the pins driving the RGB LED as outputs.
*/
static void gpio_setup(void)
{
/*
* Configure GPIOF
* This port is used to control the RGB LED
*/
periph_clock_enable(RCC_GPIOF);
const u32 outpins = (LED_R | LED_G | LED_B);
GPIO_DIR(RGB_PORT) |= outpins; /* Configure outputs. */
GPIO_DEN(RGB_PORT) |= outpins; /* Enable digital function on outputs. */
/*
* Now take care of our buttons
*/
const u32 btnpins = USR_SW1 | USR_SW2;
/*
* PF0 is locked by default. We need to unlock the GPIO_CR register,
* then enable PF0 commit. After we do this, we can setup PF0. If we
* don't do this, any configuration done to PF0 is lost, and we will not
* have a PF0 interrupt.
*/
GPIO_LOCK(GPIOF) = 0x4C4F434B;
GPIO_CR(GPIOF) |= USR_SW2;
/* Configure pins as inputs. */
GPIO_DIR(GPIOF) &= ~btnpins;
/* Enable digital function on the pins. */
GPIO_DEN(GPIOF) |= btnpins;
/* Pull-up the pins. We don't have an external pull-up */
GPIO_PUR(GPIOF) |= btnpins;
}
/* set pins as inputs so we don't interfere with an external JTAG device */
void cpld_jtag_release(void) {
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
}
void cpld_jtag_setup(void) {
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
/* TDO is an input */
GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
/* the rest are outputs */
GPIO_DIR(PORT_CPLD_TCK) |= PIN_CPLD_TCK;
GPIO_DIR(PORT_CPLD_TMS) |= PIN_CPLD_TMS;
GPIO_DIR(PORT_CPLD_TDI) |= PIN_CPLD_TDI;
}
void StaticParam_Init(void)
{
int i;
for(i = 0; i < GPIO_I2C_NUM; i ++) {
GPIO_I2C_DIR[i] = IO_ADDRESS(GPIO_DIR(GPIOGRP[i]));
GPIO_I2C_BIT[i][PINI2C_SCL] = GPIOSCL[i];
GPIO_I2C_BIT[i][PINI2C_SDA] = GPIOSDA[i];
GPIO_I2C_BIT[i][PINI2C_DAT] = GPIOSCL[i] | GPIOSDA[i];
GPIO_I2C_PIN[i][PINI2C_SCL] = IO_ADDRESS(GPIO_BASE(GPIOGRP[i]) + (GPIO_I2C_BIT[i][PINI2C_SCL] << 2));
GPIO_I2C_PIN[i][PINI2C_SDA] = IO_ADDRESS(GPIO_BASE(GPIOGRP[i]) + (GPIO_I2C_BIT[i][PINI2C_SDA] << 2));
GPIO_I2C_PIN[i][PINI2C_DAT] = IO_ADDRESS(GPIO_BASE(GPIOGRP[i]) + (GPIO_I2C_BIT[i][PINI2C_DAT] << 2));
spin_lock_init(&i2c_sem[i]);
}
#if 0
for(i = 0; i < GPIO_I2C_NUM; i ++) {
printk("------>GPIO_I2C_DIR[%d] == 0x%08X\n", i, GPIO_I2C_DIR[i]);
printk("------>GPIO_I2C_BIT[%d][%d] == 0x%08X\n", i, PINI2C_SCL, GPIO_I2C_BIT[i][PINI2C_SCL]);
printk("------>GPIO_I2C_BIT[%d][%d] == 0x%08X\n", i, PINI2C_SDA, GPIO_I2C_BIT[i][PINI2C_SDA]);
printk("------>GPIO_I2C_BIT[%d][%d] == 0x%08X\n", i, PINI2C_DAT, GPIO_I2C_BIT[i][PINI2C_DAT]);
printk("------>GPIO_I2C_PIN[%d][%d] == 0x%08X\n", i, PINI2C_SCL, GPIO_I2C_PIN[i][PINI2C_SCL]);
printk("------>GPIO_I2C_PIN[%d][%d] == 0x%08X\n", i, PINI2C_SDA, GPIO_I2C_PIN[i][PINI2C_SDA]);
printk("------>GPIO_I2C_PIN[%d][%d] == 0x%08X\n", i, PINI2C_DAT, GPIO_I2C_PIN[i][PINI2C_DAT]);
}
#endif
}
static void gpio_setup(void)
{
SYSTEMCONTROL_RCGC2 |= 0x04; /* Enable GPIOC in run mode. */
GPIO_DIR(GPIOC) |= (1 << 5); /* Configure PC5 as output. */
GPIO_DEN(GPIOC) |= (1 << 5); /* Enable digital function on PC5. */
}
static int tlmm_dump_cfg(char* buf,unsigned gpio, unsigned cfg, int output_val)
{
static char* drvstr_str[] = { "2", "4", "6", "8", "10", "12", "14", "16" }; // mA
static char* pull_str[] = { "N", "D", "K", "U" }; // "NO_PULL", "PULL_DOWN", "KEEPER", "PULL_UP"
static char* dir_str[] = { "I", "O" }; // "Input", "Output"
char func_str[20];
char* p = buf;
int drvstr = GPIO_DRVSTR(cfg);
int pull = GPIO_PULL(cfg);
int dir = GPIO_DIR(cfg);
int func = GPIO_FUNC(cfg);
//printk("%s(), drvstr=%d, pull=%d, dir=%d, func=%d\n", __func__, drvstr, pull, dir, func);
sprintf(func_str, "%d", func);
p += sprintf(p, "%d:0x%x %s%s%s%s", gpio, cfg,
func_str, pull_str[pull], dir_str[dir], drvstr_str[drvstr]);
p += sprintf(p, " = %d", output_val);
p += sprintf(p, "\n");
return p - buf;
}
static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
return 0;
}
void feldInit(){
scu_pinmux(BY_AMP_PIN,FUNC|BY_AMP_FUNC);
GPIO_DIR(BY_AMP_GPORT) |= BY_AMP_GPIN;
scu_pinmux(BY_AMP_N_PIN,FUNC|BY_AMP_N_FUNC);
GPIO_DIR(BY_AMP_N_GPORT) |= BY_AMP_N_GPIN;
SETUP(TX_AMP);
SETUP(RX_LNA);
scu_pinmux(TX_RX_PIN,FUNC|TX_RX_FUNC);
GPIO_DIR(TX_RX_GPORT) |= TX_RX_GPIN;
scu_pinmux(TX_RX_N_PIN,FUNC|TX_RX_N_FUNC);
GPIO_DIR(TX_RX_N_GPORT) |= TX_RX_N_GPIN;
scu_pinmux(BY_MIX_PIN,FUNC|BY_MIX_FUNC);
GPIO_DIR(BY_MIX_GPORT) |= BY_MIX_GPIN;
SETUP(BY_MIX_N);
scu_pinmux(LOW_HIGH_FILT_PIN,FUNC|LOW_HIGH_FILT_FUNC);
GPIO_DIR(LOW_HIGH_FILT_GPORT) |= LOW_HIGH_FILT_GPIN;
scu_pinmux(LOW_HIGH_FILT_N_PIN,FUNC|LOW_HIGH_FILT_N_FUNC);
GPIO_DIR(LOW_HIGH_FILT_N_GPORT) |= LOW_HIGH_FILT_N_GPIN;
scu_pinmux(CS_VCO_PIN,FUNC|CS_VCO_FUNC);
GPIO_DIR(CS_VCO_GPORT) |= CS_VCO_GPIN;
SETUP(MIXER_EN);
#define OFF(foo) gpio_clear(foo ## _GPORT,foo ## _GPIN);
#define ON(foo) gpio_set(foo ## _GPORT,foo ## _GPIN);
gpio_clear(BY_MIX_GPORT,BY_MIX_GPIN);
ON(BY_MIX_N);
gpio_clear(BY_AMP_GPORT,BY_AMP_GPIN);
gpio_set(BY_AMP_N_GPORT,BY_AMP_N_GPIN);
gpio_clear(TX_RX_GPORT,TX_RX_GPIN);
gpio_set(TX_RX_N_GPORT,TX_RX_N_GPIN);
gpio_clear(LOW_HIGH_FILT_GPORT,LOW_HIGH_FILT_GPIN);
gpio_set(LOW_HIGH_FILT_N_GPORT,LOW_HIGH_FILT_N_GPIN);
gpio_clear(TX_AMP_GPORT,TX_AMP_GPIN);
gpio_clear(RX_LNA_GPORT,RX_LNA_GPIN);
gpio_clear(CS_VCO_GPORT,CS_VCO_GPIN);
OFF(MIXER_EN);
};
static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
xway_gpio_set(chip, pin, val);
return 0;
}
void __gpio_tlmm_config(unsigned config)
{
uint32_t flags;
unsigned gpio = GPIO_PIN(config);
flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
__raw_writel(flags, GPIO_CONFIG(gpio));
}
/**
* \brief Configure a group of pins
*
* Sets the Pin direction, analog/digital mode, and pull-up configuration of
* or a set of GPIO pins on a given GPIO port.
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] mode Pin mode (@ref gpio_mode) \n
* - GPIO_MODE_OUTPUT -- Configure pin as output \n
* - GPIO_MODE_INPUT -- Configure pin as input \n
* - GPIO_MODE_ANALOG -- Configure pin as analog function
* @param[in] pullup Pin pullup/pulldown configuration (@ref gpio_pullup) \n
* - GPIO_PUPD_NONE -- Do not pull the pin high or low \n
* - GPIO_PUPD_PULLUP -- Pull the pin high \n
* - GPIO_PUPD_PULLDOWN -- Pull the pin low
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode,
enum gpio_pullup pullup, uint8_t gpios)
{
switch (mode) {
case GPIO_MODE_OUTPUT:
GPIO_DIR(gpioport) |= gpios;
GPIO_DEN(gpioport) |= gpios;
GPIO_AMSEL(gpioport) &= ~gpios;
break;
case GPIO_MODE_INPUT:
GPIO_DIR(gpioport) &= ~gpios;
GPIO_DEN(gpioport) |= gpios;
GPIO_AMSEL(gpioport) &= ~gpios;
break;
case GPIO_MODE_ANALOG:
GPIO_DEN(gpioport) &= ~gpios;
GPIO_AMSEL(gpioport) |= gpios;
break;
default:
/* Don't do anything */
break;
}
/*
* Setting a bit in the GPIO_PDR register clears the corresponding bit
* in the GPIO_PUR register, and vice-versa.
*/
switch (pullup) {
case GPIO_PUPD_PULLUP:
GPIO_PUR(gpioport) |= gpios;
break;
case GPIO_PUPD_PULLDOWN:
GPIO_PDR(gpioport) |= gpios;
break;
case GPIO_PUPD_NONE: /* Fall through */
default:
GPIO_PUR(gpioport) &= ~gpios;
GPIO_PDR(gpioport) &= ~gpios;
break;
}
}
void
gpio_init_inpin (unsigned int pin)
{
SYSCFG_UNLOCK;
gpio_init_pin(pin);
// set direction
GPIO_DIR(pin) |= GPIO_MASK(pin);
SYSCFG_LOCK;
}
void
gpio_init_outpin (unsigned int pin)
{
SYSCFG_UNLOCK;
gpio_init_pin(pin);
// clear pin data and set direction
GPIO_CLR(pin) = GPIO_MASK(pin);
GPIO_DIR(pin) &= ~GPIO_MASK(pin);
SYSCFG_LOCK;
}
/* --------- pinconf related code --------- */
static int xway_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *config)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
int port = PORT(pin);
u32 reg;
switch (param) {
case LTQ_PINCONF_PARAM_OPEN_DRAIN:
if (port == PORT3)
reg = GPIO3_OD;
else
reg = GPIO_OD(pin);
*config = LTQ_PINCONF_PACK(param,
!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
break;
case LTQ_PINCONF_PARAM_PULL:
if (port == PORT3)
reg = GPIO3_PUDEN;
else
reg = GPIO_PUDEN(pin);
if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
*config = LTQ_PINCONF_PACK(param, 0);
break;
}
if (port == PORT3)
reg = GPIO3_PUDSEL;
else
reg = GPIO_PUDSEL(pin);
if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
*config = LTQ_PINCONF_PACK(param, 2);
else
*config = LTQ_PINCONF_PACK(param, 1);
break;
case LTQ_PINCONF_PARAM_OUTPUT:
reg = GPIO_DIR(pin);
*config = LTQ_PINCONF_PACK(param,
gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
break;
default:
dev_err(pctldev->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
return 0;
}
int gpio_tlmm_config(unsigned config, unsigned disable)
{
uint32_t flags;
unsigned gpio = GPIO_PIN(config);
if (gpio > NR_MSM_GPIOS)
return -EINVAL;
flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
writel(flags, GPIO_CONFIG(gpio));
return 0;
}
adc_init (void)
{
// init adc power pins
gpio_init_pin(GPIO_PIN(6, 14)); // 5VONIGEN
gpio_init_pin(GPIO_PIN(0, 6)); // ADCBATEN
// enable battery power on adc
GPIO_SET(GPIO_PIN(0, 6)) = GPIO_MASK(GPIO_PIN(0, 6));
GPIO_DIR(GPIO_PIN(0, 6)) &= ~GPIO_MASK(GPIO_PIN(0, 6));
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
spi_update(0x400F);
}
int gpio_tlmm_config(unsigned config, unsigned disable)
{
uint32_t v2flags;
unsigned long irq_flags;
unsigned gpio = GPIO_PIN(config);
if (gpio > NR_MSM_GPIOS)
return -EINVAL;
v2flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
spin_lock_irqsave(&gpio_lock, irq_flags);
writel(v2flags, GPIO_CONFIG(gpio));
spin_unlock_irqrestore(&gpio_lock, irq_flags);
return 0;
}
static int tlmm_get_cfg(unsigned gpio, unsigned* cfg)
{
unsigned flags;
BUG_ON(gpio >= TLMM_NUM_GPIO);
//printk("%s(), gpio=%d, addr=0x%08x\n", __func__, gpio, (unsigned int)GPIO_CONFIG(gpio));
#if 0
flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
#else
flags = __raw_readl(GPIO_CONFIG(gpio));
#endif
*cfg = GPIO_CFG(gpio, (flags >> 2) & 0xf, (flags >> 9) & 0x1, flags & 0x3, (flags >> 6) & 0x7);
return 0;
}
void rf_path_pin_setup() {
#ifdef HACKRF_ONE
/* Configure RF switch control signals */
scu_pinmux(SCU_HP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_LP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_NO_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_NO_TX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_AMP_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/* Configure RF power supply (VAA) switch */
scu_pinmux(SCU_NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/* Configure RF switch control signals as outputs */
GPIO0_DIR |= PIN_AMP_BYPASS;
GPIO1_DIR |= (PIN_NO_MIX_BYPASS | PIN_RX_AMP | PIN_NO_RX_AMP_PWR);
GPIO2_DIR |= (PIN_HP | PIN_LP | PIN_TX_MIX_BP | PIN_RX_MIX_BP | PIN_TX_AMP);
GPIO3_DIR |= PIN_NO_TX_AMP_PWR;
GPIO5_DIR |= (PIN_TX | PIN_MIX_BYPASS | PIN_RX);
/*
* Safe (initial) switch settings turn off both amplifiers and antenna port
* power and enable both amp bypass and mixer bypass.
*/
switchctrl_set(SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_MIX_BYPASS);
/* Configure RF power supply (VAA) switch control signal as output */
GPIO_DIR(PORT_NO_VAA_ENABLE) |= PIN_NO_VAA_ENABLE;
/* Safe state: start with VAA turned off: */
disable_rf_power();
#endif
}
void tlmm_before_sleep_set_configs(void)
{
int res;
unsigned i;
//only set tlmms before sleep when it's enabled
if (!before_sleep_table_enabled)
return;
printk("%s(), before_sleep_table_enabled=%d\n", __func__, before_sleep_table_enabled);
for(i = 0; i < TLMM_NUM_GPIO; ++i) {
unsigned cfg;
int gpio;
int dir;
int func;
int output_val = 0;
cfg = before_sleep_table_configs[i];
gpio = GPIO_PIN(cfg);
if(gpio != i)//(cfg & ~0x20000000) == 0 ||
continue;
output_val = HAL_OUTPUT_VAL(cfg);
//Clear the output value
//cfg &= ~0x40000000;
dir = GPIO_DIR(cfg);
func = GPIO_FUNC(cfg);
printk("%s(), [%d]: 0x%x\n", __func__, i, cfg);
res = gpio_tlmm_config((cfg & ~0x40000000), GPIO_CFG_ENABLE);
if(res < 0) {
printk("Error: Config failed.\n");
}
if((func == 0) && (dir == 1)) // gpio output
__msm_gpio_set_inout(i, output_val);
}
}
static inline void lpc43_configoutput(uint16_t gpiocfg,
unsigned int port, unsigned int pin)
{
uintptr_t regaddr;
uint32_t regval;
/* Then configure the pin as an output by setting the corresponding
* bit in the GPIO DIR register for the port.
*/
regaddr = LPC43_GPIO_DIR(port);
regval = getreg32(regaddr);
regval |= GPIO_DIR(pin);
putreg32(regval, regaddr);
/* Set the initial value of the output */
lpc43_gpio_write(gpiocfg, GPIO_IS_ONE(gpiocfg));
/* To be able to read the signal on the GPIO input, the input
* buffer must be enabled in the syscon block for the corresponding pin.
* This should have been done when the pin was configured as a GPIO.
*/
}
int msm_gpios_disable(const struct msm_gpio *table, int size)
{
int rc = 0;
int i;
const struct msm_gpio *g;
for (i = size-1; i >= 0; i--) {
int tmp;
g = table + i;
tmp = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_DISABLE);
if (tmp) {
pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_DISABLE)"
" <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
if (!rc)
rc = tmp;
}
}
return rc;
}
int msm_gpios_enable(const struct msm_gpio *table, int size)
{
int rc;
int i;
const struct msm_gpio *g;
for (i = 0; i < size; i++) {
g = table + i;
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_ENABLE);
if (rc) {
pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_ENABLE)"
" <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
goto err;
}
}
return 0;
err:
msm_gpios_disable(table, i);
return rc;
}
void iomux_debug_set(void)
{
int i = 0;
unsigned int uregv = 0;
struct iocfg_lp *iocfg_lookups = NULL;
get_active_io_cfglp();
iocfg_lookups = p_active_io_cfglp;
for (i = 0; i < IO_LIST_LENGTH; i++) {
uregv = ((iocfg_lookups[i].ugpiog<<3)+iocfg_lookups[i].ugpio_bit);
/*uart0 suspend printk*/
if ((0 == console_suspend_enabled)
&& ((uregv >= 117) && (uregv <= 120)))
continue;
if (E_BOARD_TYPE_PLATFORM == get_board_type()) {
/*oem board*/
if ((uregv == 40) || (uregv == 83))
continue;
if ((uregv >= 129) && (uregv <= 132))
continue;
if ((uregv >= 137) && (uregv <= 140))
continue;
} else {
if ((uregv == 145) || (uregv == 146))
continue;
}
uregv = readl(IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
if (iocfg_lookups[i].iomg_val != -1) {
if ((uregv&0x1) == iocfg_lookups[i].iomg_val)
writel(uregv, IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
else
writel(iocfg_lookups[i].iomg_val, IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
}
uregv = readl(IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
if (iocfg_lookups[i].iocg_val != -1) {
if ((uregv&0x3) == iocfg_lookups[i].iocg_val)
writel(uregv, IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
else
writel(iocfg_lookups[i].iocg_val, IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
}
uregv = readl(GPIO_DIR(iocfg_lookups[i].ugpiog));
uregv &= ~GPIO_BIT(1, iocfg_lookups[i].ugpio_bit);
uregv |= GPIO_BIT(iocfg_lookups[i].gpio_dir, iocfg_lookups[i].ugpio_bit);
writel(uregv, GPIO_DIR(iocfg_lookups[i].ugpiog));
uregv = readl(GPIO_DIR(iocfg_lookups[i].ugpiog));
uregv = readl(GPIO_DATA(iocfg_lookups[i].ugpiog));
uregv &= ~GPIO_BIT(1, iocfg_lookups[i].ugpio_bit);
uregv |= GPIO_BIT(iocfg_lookups[i].gpio_val, iocfg_lookups[i].ugpio_bit);
writel(uregv, GPIO_DATA(iocfg_lookups[i].ugpiog));
}
}
void iomux_debug_show(int check)
{
int i = 0;
int iflg = 0;
unsigned int uregv = 0;
struct iocfg_lp *iocfg_lookups = NULL;
get_active_io_cfglp();
iocfg_lookups = p_active_io_cfglp;
for (i = 0; i < IO_LIST_LENGTH; i++) {
iflg = 0;
printk("GPIO_%02d_%d (%03d) ",\
iocfg_lookups[i].ugpiog, iocfg_lookups[i].ugpio_bit,\
((iocfg_lookups[i].ugpiog<<3)+iocfg_lookups[i].ugpio_bit));
uregv = readl(IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
printk("IOMG=0x%02X ", uregv);
if (check == 1) {
if ((uregv == iocfg_lookups[i].iomg_val)\
|| (-1 == iocfg_lookups[i].iomg_val))
printk("(0x%02X) ", (unsigned char)uregv);
else {
iflg = 1;
printk("(0x%02X) ", (unsigned char)iocfg_lookups[i].iomg_val);
}
}
uregv = readl(IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
printk("IOCG=0x%02X ", uregv);
if (check == 1) {
if (((uregv & 0x3) == iocfg_lookups[i].iocg_val)\
|| (-1 == iocfg_lookups[i].iocg_val))
printk("(0x%02X) ", (unsigned char)uregv);
else {
iflg = 1;
printk("(0x%02X) ", (unsigned char)iocfg_lookups[i].iocg_val);
}
}
uregv = readl(GPIO_DIR(iocfg_lookups[i].ugpiog));
printk("DIR=0x%02X ", GPIO_IS_SET(iocfg_lookups[i].ugpio_bit));
if (check == 1) {
if ((uregv & GPIO_BIT(1, iocfg_lookups[i].ugpio_bit))\
== (GPIO_BIT(iocfg_lookups[i].gpio_dir, iocfg_lookups[i].ugpio_bit)))
printk("(0x%02X) ", GPIO_IS_SET(iocfg_lookups[i].ugpio_bit));
else {
iflg = 1;
printk("(0x%02X) ", (unsigned char)iocfg_lookups[i].gpio_dir);
}
}
uregv = readl(GPIO_DATA(iocfg_lookups[i].ugpiog));
printk("VAL=0x%02X ", GPIO_IS_SET(iocfg_lookups[i].ugpio_bit));
if (check == 1) {
if (((uregv & GPIO_BIT(1, iocfg_lookups[i].ugpio_bit))\
== GPIO_BIT(iocfg_lookups[i].gpio_val, iocfg_lookups[i].ugpio_bit))\
|| (uregv & GPIO_BIT(iocfg_lookups[i].iocg_val, iocfg_lookups[i].ugpio_bit)))
printk("(0x%02X) ", GPIO_IS_SET(iocfg_lookups[i].ugpio_bit));
else {
iflg = 1;
printk("(0x%02X) ", (unsigned char)iocfg_lookups[i].gpio_val);
}
}
if (iflg == 1)
printk("e");
printk("\n");
}
}
static int xway_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
enum ltq_pinconf_param param;
int arg;
int port = PORT(pin);
u32 reg;
int i;
for (i = 0; i < num_configs; i++) {
param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
switch (param) {
case LTQ_PINCONF_PARAM_OPEN_DRAIN:
if (port == PORT3)
reg = GPIO3_OD;
else
reg = GPIO_OD(pin);
if (arg == 0)
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
else
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
case LTQ_PINCONF_PARAM_PULL:
if (port == PORT3)
reg = GPIO3_PUDEN;
else
reg = GPIO_PUDEN(pin);
if (arg == 0) {
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
}
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
if (port == PORT3)
reg = GPIO3_PUDSEL;
else
reg = GPIO_PUDSEL(pin);
if (arg == 1)
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
else if (arg == 2)
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
else
dev_err(pctldev->dev,
"Invalid pull value %d\n", arg);
break;
case LTQ_PINCONF_PARAM_OUTPUT:
reg = GPIO_DIR(pin);
if (arg == 0)
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
else
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
default:
dev_err(pctldev->dev,
"Invalid config param %04x\n", param);
return -ENOTSUPP;
}
} /* for each config */
return 0;
}
/* config modem pintrl status */
void pintrl_config(struct pintrl_stru *iocfg_stru, unsigned int length)
{
unsigned int i;
unsigned int uregv, value, value1, addr, addr1;
if(NULL == iocfg_stru || (0 == length))
{
return;
}
for (i = 0; i < length; i++) {
//pintrl_data_convert(&iocfg_stru, &(iocfg_table[i]));
uregv = ((iocfg_stru[i].ugpiog << 3) + iocfg_stru[i].ugpio_bit);
/* set iomg register */
if (0xfff != iocfg_stru[i].uiomg_off) {
value = iocfg_stru[i].iomg_val;
if (uregv <= 164) {
addr = HI_PINTRL_REG_ADDR + (iocfg_stru[i].uiomg_off);
} else {
addr = HI_PINTRL_SYS_REG_ADDR + (iocfg_stru[i].uiomg_off);
}
writel(value, addr);
}
/* set iocg register */
if (uregv <= 164) {
addr = HI_PINTRL_REG_ADDR + 0x800 + (iocfg_stru[i].uiocg_off);
} else {
addr = HI_PINTRL_SYS_REG_ADDR + 0x800 + (iocfg_stru[i].uiocg_off);
}
value = readl(addr) & (~0x03);
writel(value | iocfg_stru[i].iocg_val, addr);
/* gpio controller register */
if (!iocfg_stru[i].iomg_val) {
if (!iocfg_stru[i].gpio_dir) { /* direction is in */
if (uregv <= 164) {
addr = GPIO_DIR(iocfg_stru[i].ugpiog);
} else {
addr = GPIO_SYS_DIR(iocfg_stru[i].ugpiog);
}
value = readl(addr) & (~(GPIO_BIT(1, iocfg_stru[i].ugpio_bit)));
writel(value, addr);
} else { /* direction is out */
if (uregv <= 164) {
addr = GPIO_DIR(iocfg_stru[i].ugpiog);
addr1 = GPIO_DATA(iocfg_stru[i].ugpiog, iocfg_stru[i].ugpio_bit);
} else {
addr = GPIO_SYS_DIR(iocfg_stru[i].ugpiog);
addr1= GPIO_SYS_DATA(iocfg_stru[i].ugpiog, iocfg_stru[i].ugpio_bit);
}
value = readl(addr) | GPIO_BIT(1, iocfg_stru[i].ugpio_bit);
value1 = GPIO_BIT(iocfg_stru[i].gpio_val, iocfg_stru[i].ugpio_bit);
writel(value, addr);
writel(value1, addr1);
}
}
}
}
int main(void)
{
cpu_clock_init_();
// cpu_clock_pll1_max_speed();
scu_pinmux(RF_EN_PIN,SCU_GPIO_NOPULL|RF_EN_FUNC);
GPIO_DIR(RF_EN_GPORT) |= RF_EN_GPIN;
gpio_clear(RF_EN_GPORT, RF_EN_GPIN); /* RF off */
// Config LED as out
scu_pinmux(LED1_PIN,SCU_GPIO_NOPULL|LED1_FUNC);
GPIO_DIR(LED1_GPORT) |= LED1_GPIN;
inputInit();
lcdInit();
lcdFill(0xff);
setSystemFont();
char tu=0,td=0,tl=0,tr=0,tm=0;
char led=0;
lcdPrintln("Sec-Test v2");
lcdPrintln("");
int ctr=0;
int k=0;
/* Blink LED1 on the board. */
while (1)
{
lcdSetCrsr(0,16);
lcdPrint(IntToStr(tu,2,F_HEX)); lcdPrintln(" Up");
lcdPrint(IntToStr(td,2,F_HEX)); lcdPrintln(" Down");
lcdPrint(IntToStr(tl,2,F_HEX)); lcdPrintln(" Left");
lcdPrint(IntToStr(tr,2,F_HEX)); lcdPrintln(" Right");
lcdPrint(IntToStr(tm,2,F_HEX)); lcdPrintln(" Enter");
lcdDisplay();
switch(getInput()){
case BTN_UP:
tu=1-tu;
if (tu){
}else{
};
break;
case BTN_DOWN:
td=1-td;
if (td){
}else{
};
break;
case BTN_LEFT:
tl=1-tl;
if (tl){
}else{
};
break;
case BTN_RIGHT:
tr=1-tr;
if (tr){
}else{
};
break;
case BTN_ENTER:
tm=1-tm;
if (tm){
}else{
};
break;
};
led=1-led;
if (led){
gpio_set(LED1_GPORT, LED1_GPIN); /* LED on */
}else{
gpio_clear(LED1_GPORT, LED1_GPIN); /* LED off */
// delayNop(200000);
};
ctr++;
lcdNl();
lcdPrint(IntToStrX(ctr,4));
}
return 0;
}
