/* Now put those constants into the correct registers */
static void setup_data_fifos(void)
{
int i;
print_later("setup_data_fifos()", 0, 0, 0, 0, 0);
/* Programmer's Guide, p31 */
GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */
GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */
/* TXFIFO 1..15 */
for (i = 1; i < MAX_NORMAL_EPS; i++)
GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) |
(RXFIFO_SIZE + i * TXFIFO_SIZE));
/*
* TODO: The Programmer's Guide is confusing about when or whether to
* flush the FIFOs. Section 2.1.1.2 (p31) just says to flush. Section
* 2.2.2 (p55) says to stop all the FIFOs first, then flush. Section
* 7.5.4 (p162) says that flushing the RXFIFO at reset is not
* recommended at all.
*
* I'm also unclear on whether or not the individual EPs are expected
* to be disabled already (DIEPCTLn/DOEPCTLn.EPENA == 0), and if so,
* whether by firmware or hardware.
*/
/* Flush all FIFOs according to Section 2.1.1.2 */
GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH;
while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
; /* TODO: timeout 100ms */
}
static void flush_in_fifo(void)
{
/* TODO: Programmer's Guide p167 suggests lots more stuff */
GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0) | GRSTCTL_TXFFLSH;
while (GR_USB_GRSTCTL & GRSTCTL_TXFFLSH)
; /* timeout? */
}
static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
stm32_otg_t *otgp = usbp->otg;
otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
;
/* Wait for 3 PHY Clocks.*/
halPolledDelay(12);
}
void Usb_t::TxFifoFlush() {
// Uart.Printf("TxFlush1: %X %X\r\n", OTG_FS->GRSTCTL, OTG_FS->GINTSTS);
// if(!(OTG_FS->GINTSTS & GINTSTS_GINAKEFF)) OTG_FS->DCTL |= DCTL_SGINAK;
// while(!(OTG_FS->GINTSTS & GINTSTS_GINAKEFF));
// Uart.Printf("TxFlush2: %X %X\r\n", OTG_FS->GRSTCTL, OTG_FS->GINTSTS);
OTG_FS->GRSTCTL = GRSTCTL_TXFNUM(0) | GRSTCTL_TXFFLSH;
while((OTG_FS->GRSTCTL & GRSTCTL_TXFFLSH) != 0);
// Wait for 3 PHY Clocks
__NOP();
__NOP();
// OTG_FS->DCTL |= DCTL_CGINAK;
}