/** * Should Low Power P-state be enabled * If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE Low Power P-state is supported. * @retval FALSE Low Power P-state cannot be enabled. * */ BOOLEAN STATIC IsLowPwrPstateFeatureSupported ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; BOOLEAN IsSupported; LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; IsSupported = FALSE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { IsSupported = TRUE; } else { IsSupported = FALSE; break; } } else { IsSupported = FALSE; break; } } } IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader); return IsSupported; }
/** * Should CPB be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE CPB is supported. * @retval FALSE CPB cannot be enabled. * */ BOOLEAN STATIC IsCpbFeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; BOOLEAN IsEnabled; CPB_FAMILY_SERVICES *FamilyServices; IsEnabled = FALSE; ASSERT (PlatformConfig->CpbMode < MaxCpbMode); if (PlatformConfig->CpbMode == CpbModeAuto) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { IsEnabled = TRUE; break; } } } } } return IsEnabled; }
/** * Should IO Cstate be enabled * If all processors support IO Cstate, return TRUE. Otherwise, return FALSE * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE IO Cstate is supported. * @retval FALSE IO Cstate cannot be enabled. * */ BOOLEAN STATIC IsIoCstateFeatureSupported ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; BOOLEAN IsSupported; IO_CSTATE_FAMILY_SERVICES *IoCstateServices; IsSupported = FALSE; if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (CONST VOID **)&IoCstateServices, StdHeader); if (IoCstateServices != NULL) { if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) { IsSupported = TRUE; } else { // Stop checking remaining socket(s) once we find one that does not support IO Cstates IsSupported = FALSE; break; } } else { // Exit the for loop if we found a socket that does not have the IO Cstates feature installed IsSupported = FALSE; break; } } } } return IsSupported; }
/** * Should L3 features be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE L3 Features are supported * @retval FALSE L3 Features are not supported * */ BOOLEAN STATIC IsL3FeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { BOOLEAN IsEnabled; UINT32 Socket; L3_FEATURE_FAMILY_SERVICES *FamilyServices; IsEnabled = FALSE; if (PlatformConfig->PlatformProfile.UseHtAssist || PlatformConfig->PlatformProfile.UseAtmMode) { IsEnabled = TRUE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (const VOID **) &FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsL3FeatureSupported (FamilyServices, Socket, StdHeader)) { IsEnabled = FALSE; break; } } } } return IsEnabled; }
/** * Enable core performance boost * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval AGESA_SUCCESS Always succeeds. * */ AGESA_STATUS STATIC InitializeCpbFeature ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; AGESA_STATUS AgesaStatus; AGESA_STATUS CalledStatus; CPB_FAMILY_SERVICES *FamilyServices; AgesaStatus = AGESA_SUCCESS; CalledStatus = AGESA_SUCCESS; IDS_HDT_CONSOLE (CPU_TRACE, " Boost is enabled\n"); for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader); if (CalledStatus > AgesaStatus) { AgesaStatus = CalledStatus; } } } } } return AgesaStatus; }
/** * Should P-state HPC mode be enabled * If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE P-state HPC mode is supported. * @retval FALSE P-state HPC mode cannot be enabled. * */ BOOLEAN STATIC IsPstateHpcModeFeatureSupported ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { BOOLEAN IsEnabled; UINT32 Socket; PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices; IsEnabled = TRUE; if (PlatformConfig->PStatesInHpcMode) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&PstateHpcModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); if (FamilyServices == NULL) { IsEnabled = FALSE; break; } } } } else { IsEnabled = FALSE; } return IsEnabled; }
/** * Should C6 be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE C6 is supported. * @retval FALSE C6 cannot be enabled. * */ BOOLEAN STATIC IsC6FeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; BOOLEAN IsEnabled; C6_FAMILY_SERVICES *FamilyServices; IsEnabled = FALSE; if (PlatformConfig->CStateMode == CStateModeC6) { IsEnabled = TRUE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) { IsEnabled = FALSE; break; } } } } return IsEnabled; }
/** * Should Application Power Management (APM) be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE APM is supported. * @retval FALSE APM cannot be enabled. * */ STATIC BOOLEAN IsApmFeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; BOOLEAN IsEnabled; APM_FAMILY_SERVICES *FamilyServices; IsEnabled = FALSE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&ApmFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsApmSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { IsEnabled = TRUE; break; } } } } return IsEnabled; }
/** * * InitializeCacheFlushOnHaltFeature * * CPU feature leveling. Enable Cpu Cache Flush On Halt Function * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct. * * @return The most severe status of any family specific service. */ STATIC AGESA_STATUS InitializeCacheFlushOnHaltFeature ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN OUT AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; UINT32 Module; UINT32 AndMask; UINT32 OrMask; UINT32 PciRegister; PCI_ADDR PciAddress; PCI_ADDR CfohPciAddress; AGESA_STATUS AgesaStatus; CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices; ASSERT (IsBsp (StdHeader, &AgesaStatus)); FamilySpecificServices = NULL; AndMask = 0xFFFFFFFF; OrMask = 0x00000000; PciRegister = 0; AgesaStatus = AGESA_SUCCESS; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { // Get services for the socket GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); if (FamilySpecificServices != NULL) { FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader); // Get the Or Mask value from IDS IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader); // Set Cache Flush On Halt register for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { PciAddress.Address.Function = CfohPciAddress.Address.Function; PciAddress.Address.Register = CfohPciAddress.Address.Register; LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); PciRegister &= AndMask; PciRegister |= OrMask; LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); } } } } } return AgesaStatus; }
/** * * CpuPrefetchModeApTask * * Parameters: * @param[in] ApExeParams Handle to config for library and services. * * @retval AGESA_STATUS * * Processing: * */ AGESA_STATUS CpuPrefetchModeApTask ( IN AP_EXE_PARAMS *ApExeParams ) { UINT32 Socket; UINT32 Module; UINT32 Core; AGESA_STATUS IgnoredSts; AGESA_STATUS CalledStatus; PREFETCH_MODE_FAMILY_SERVICES *FamilyServices; CalledStatus = AGESA_ERROR; IdentifyCore (&(ApExeParams->StdHeader), &Socket, &Module, &Core, &IgnoredSts); GetFeatureServicesOfSocket (&PrefetchModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, &(ApExeParams->StdHeader)); if (FamilyServices != NULL) { CalledStatus = FamilyServices->PrefetchModeControlOnCore (FamilyServices, (PLATFORM_CONFIGURATION *) (ApExeParams->RelatedDataBlock), &(ApExeParams->StdHeader)); } return CalledStatus; }
/** * Should message-based C1e be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE Message-based C1e is supported. * @retval FALSE Message-based C1e cannot be enabled. * */ BOOLEAN STATIC IsMsgBasedC1eFeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { BOOLEAN IsEnabled; UINT32 Socket; MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; ASSERT (PlatformConfig->C1eMode < MaxC1eMode); IsEnabled = FALSE; if ((PlatformConfig->C1eMode == C1eModeMsgBased) || (PlatformConfig->C1eMode == C1eModeAuto)) { ASSERT (PlatformConfig->C1ePlatformData < 0x10000); ASSERT (PlatformConfig->C1ePlatformData != 0); if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) { IsEnabled = TRUE; if (IsNonCoherentHt1 (StdHeader)) { IsEnabled = FALSE; } else { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) { IsEnabled = FALSE; break; } } } } } } return IsEnabled; }
/** * Should Power Status Indicator (PSI) be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE PSI is supported. * @retval FALSE PSI cannot be enabled. * */ BOOLEAN STATIC IsPsiFeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Socket; BOOLEAN IsEnabled; PSI_FAMILY_SERVICES *PsiFamilyServices; UINT32 VrmType; IsEnabled = FALSE; for (VrmType = 0; VrmType < MaxVrmType; VrmType++) { if (PlatformConfig->VrmProperties[VrmType].LowPowerThreshold != 0) { IsEnabled = TRUE; break; } } if (!IsEnabled) { return FALSE; } for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&PsiFamilyServiceTable, Socket, (CONST VOID **)&PsiFamilyServices, StdHeader); if ((PsiFamilyServices == NULL) || (!PsiFamilyServices->IsPsiSupported (PsiFamilyServices, Socket, PlatformConfig, StdHeader))) { IsEnabled = FALSE; break; } } } return IsEnabled; }
/** * Performs core leveling for the system. * * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter. * The possible modes are: * -0 CORE_LEVEL_LOWEST Level to lowest common denominator * -1 CORE_LEVEL_TWO Level to 2 cores * -2 CORE_LEVEL_POWER_OF_TWO Level to 1,2,4 or 8 * -3 CORE_LEVEL_NONE Do no leveling * -4 CORE_LEVEL_COMPUTE_UNIT Level cores to one core per compute unit * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the leveling mode parameter * @param[in] StdHeader Config handle for library and services * * @return The most severe status of any family specific service. * */ AGESA_STATUS CoreLevelingAtEarly ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 CoreNumPerComputeUnit; UINT32 MinNumOfComputeUnit; UINT32 EnabledComputeUnit; UINT32 Socket; UINT32 Module; UINT32 NumberOfSockets; UINT32 NumberOfModules; UINT32 MinCoreCountOnNode; UINT32 MaxCoreCountOnNode; UINT32 LowCore; UINT32 HighCore; UINT32 LeveledCores; UINT32 RequestedCores; UINT32 TotalEnabledCoresOnNode; BOOLEAN RegUpdated; AP_MAIL_INFO ApMailboxInfo; CORE_LEVELING_TYPE CoreLevelMode; CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices; WARM_RESET_REQUEST Request; MaxCoreCountOnNode = 0; MinCoreCountOnNode = 0xFFFFFFFF; LeveledCores = 0; CoreNumPerComputeUnit = 1; MinNumOfComputeUnit = 0xFF; ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax); // Get OEM IO core level mode CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; // Get socket count NumberOfSockets = GetPlatformNumberOfSockets (); GetApMailbox (&ApMailboxInfo.Info, StdHeader); NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1; // Collect cpu core info for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { for (Module = 0; Module < NumberOfModules; Module++) { if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { // Get the highest and lowest core count in all nodes TotalEnabledCoresOnNode = HighCore - LowCore + 1; if (TotalEnabledCoresOnNode < MinCoreCountOnNode) { MinCoreCountOnNode = TotalEnabledCoresOnNode; } if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) { MaxCoreCountOnNode = TotalEnabledCoresOnNode; } EnabledComputeUnit = TotalEnabledCoresOnNode; switch (GetComputeUnitMapping (StdHeader)) { case AllCoresMapping: // All cores are in their own compute unit. break; case EvenCoresMapping: // Cores are paired in compute units. CoreNumPerComputeUnit = 2; EnabledComputeUnit = (TotalEnabledCoresOnNode / 2); break; default: ASSERT (FALSE); } // Get minimum of compute unit. This will either be the minimum number of cores (AllCoresMapping), // or less (EvenCoresMapping). if (EnabledComputeUnit < MinNumOfComputeUnit) { MinNumOfComputeUnit = EnabledComputeUnit; } } } } } // Get LeveledCores switch (CoreLevelMode) { case CORE_LEVEL_LOWEST: if (MinCoreCountOnNode == MaxCoreCountOnNode) { return (AGESA_SUCCESS); } LeveledCores = (MinCoreCountOnNode / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; break; case CORE_LEVEL_TWO: LeveledCores = 2 / NumberOfModules; if (LeveledCores != 0) { LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; } else { return (AGESA_WARNING); } if ((LeveledCores * NumberOfModules) != 2) { PutEventLog ( AGESA_WARNING, CPU_WARNING_ADJUSTED_LEVELING_MODE, 2, (LeveledCores * NumberOfModules), 0, 0, StdHeader ); } break; case CORE_LEVEL_POWER_OF_TWO: // Level to power of 2 (1, 2, 4, 8...) LeveledCores = 1; while (MinCoreCountOnNode >= (LeveledCores * 2)) { LeveledCores = LeveledCores * 2; } break; case CORE_LEVEL_COMPUTE_UNIT: // Level cores to one core per compute unit, with additional reduction to level // all processors to match the processor with the minimum number of cores. if (CoreNumPerComputeUnit == 1) { // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST. if (MinCoreCountOnNode == MaxCoreCountOnNode) { return (AGESA_SUCCESS); } LeveledCores = MinCoreCountOnNode; } else { // If there are more than one core per compute unit, level to the number of compute units. LeveledCores = MinNumOfComputeUnit; } break; case CORE_LEVEL_ONE: LeveledCores = 1; if (NumberOfModules > 1) { PutEventLog ( AGESA_WARNING, CPU_WARNING_ADJUSTED_LEVELING_MODE, 1, NumberOfModules, 0, 0, StdHeader ); } break; case CORE_LEVEL_THREE: case CORE_LEVEL_FOUR: case CORE_LEVEL_FIVE: case CORE_LEVEL_SIX: case CORE_LEVEL_SEVEN: case CORE_LEVEL_EIGHT: case CORE_LEVEL_NINE: case CORE_LEVEL_TEN: case CORE_LEVEL_ELEVEN: case CORE_LEVEL_TWELVE: case CORE_LEVEL_THIRTEEN: case CORE_LEVEL_FOURTEEN: case CORE_LEVEL_FIFTEEN: // MCM processors can not have an odd number of cores. For an odd CORE_LEVEL_N, MCM processors will be // leveled as though CORE_LEVEL_N+1 was chosen. // Processors with compute units disable all cores in an entire compute unit at a time, or on an MCM processor, // two compute units at a time. For example, on an SCM processor with two cores per compute unit, the effective // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and // CORE_LEVEL_EIGHT. The same example for an MCM processor with two cores per compute unit has effective // explicit levels of CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_EIGHT, and CORE_LEVEL_TWELVE. RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3; LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules; LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; if (LeveledCores != 1) { LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; } if ((LeveledCores * NumberOfModules * CoreNumPerComputeUnit) != RequestedCores) { PutEventLog ( AGESA_WARNING, CPU_WARNING_ADJUSTED_LEVELING_MODE, RequestedCores, (LeveledCores * NumberOfModules * CoreNumPerComputeUnit), 0, 0, StdHeader ); } break; default: ASSERT (FALSE); } // Set down core register for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader); if (FamilySpecificServices != NULL) { for (Module = 0; Module < NumberOfModules; Module++) { RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader); // If the down core register is updated, trigger a warm reset. if (RegUpdated) { GetWarmResetFlag (StdHeader, &Request); Request.RequestBit = TRUE; Request.StateBits = Request.PostStage - 1; SetWarmResetFlag (StdHeader, &Request); } } } } } return (AGESA_SUCCESS); }
/** * Performs core leveling for the system. * * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter. * The possible modes are: * -0 CORE_LEVEL_LOWEST Level to lowest common denominator * -1 CORE_LEVEL_TWO Level to 2 cores * -2 CORE_LEVEL_POWER_OF_TWO Level to 1,2,4 or 8 * -3 CORE_LEVEL_NONE Do no leveling * -4 CORE_LEVEL_COMPUTE_UNIT Level cores to one core per compute unit * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the leveling mode parameter * @param[in] StdHeader Config handle for library and services * * @return The most severe status of any family specific service. * */ AGESA_STATUS CoreLevelingAtEarly ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 CoreNumPerComputeUnit; UINT32 EnabledComputeUnit; UINT32 SocketAndModule; UINT32 LowCore; UINT32 HighCore; UINT32 LeveledCores; UINT32 RequestedCores; UINT32 TotalEnabledCoresOnNode; BOOLEAN RegUpdated; CORE_LEVELING_TYPE CoreLevelMode; CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices; WARM_RESET_REQUEST Request; IDS_HDT_CONSOLE (CPU_TRACE, "CoreLevelingAtEarly\n CoreLevelMode: %d\n", PlatformConfig->CoreLevelingMode); LeveledCores = 0; SocketAndModule = 0; ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax); // Get OEM IO core level mode CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; // Collect cpu core info GetGivenModuleCoreRange (0, 0, &LowCore, &HighCore, StdHeader); // Get the highest and lowest core count in all nodes TotalEnabledCoresOnNode = HighCore - LowCore + 1; switch (GetComputeUnitMapping (StdHeader)) { case AllCoresMapping: // All cores are in their own compute unit. CoreNumPerComputeUnit = 1; EnabledComputeUnit = TotalEnabledCoresOnNode; break; case EvenCoresMapping: // Cores are paired in compute units. CoreNumPerComputeUnit = 2; EnabledComputeUnit = (TotalEnabledCoresOnNode / 2); break; case TripleCoresMapping: // Three cores are grouped in compute units. CoreNumPerComputeUnit = 3; EnabledComputeUnit = (TotalEnabledCoresOnNode / 3); break; case QuadCoresMapping: // Four cores are grouped in compute units. CoreNumPerComputeUnit = 4; EnabledComputeUnit = (TotalEnabledCoresOnNode / 4); break; default: CoreNumPerComputeUnit = 1; EnabledComputeUnit = TotalEnabledCoresOnNode; ASSERT (FALSE); } IDS_HDT_CONSOLE (CPU_TRACE, " TotalEnabledCoresOnNode %d EnabledComputeUnit %d\n", \ TotalEnabledCoresOnNode, EnabledComputeUnit); // Get LeveledCores switch (CoreLevelMode) { case CORE_LEVEL_LOWEST: return (AGESA_SUCCESS); break; case CORE_LEVEL_TWO: LeveledCores = 2; LeveledCores = (LeveledCores <= TotalEnabledCoresOnNode) ? LeveledCores : TotalEnabledCoresOnNode; if (LeveledCores != 2) { PutEventLog ( AGESA_WARNING, CPU_WARNING_ADJUSTED_LEVELING_MODE, 2, LeveledCores, 0, 0, StdHeader ); } break; case CORE_LEVEL_POWER_OF_TWO: // Level to power of 2 (1, 2, 4, 8...) LeveledCores = 1; while (TotalEnabledCoresOnNode >= (LeveledCores * 2)) { LeveledCores = LeveledCores * 2; } break; case CORE_LEVEL_COMPUTE_UNIT: case CORE_LEVEL_COMPUTE_UNIT_TWO: case CORE_LEVEL_COMPUTE_UNIT_THREE: // Level cores to 1~3 core(s) per compute unit, with additional reduction to level // all processors to match the processor with the minimum number of cores. if (CoreNumPerComputeUnit == 1) { // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST. return (AGESA_SUCCESS); } else { // If there are more than one core per compute unit, level to the number of compute units * cores per compute unit. LeveledCores = EnabledComputeUnit * (CoreLevelMode - CORE_LEVEL_COMPUTE_UNIT + 1); } break; case CORE_LEVEL_ONE: LeveledCores = 1; break; case CORE_LEVEL_THREE: case CORE_LEVEL_FOUR: case CORE_LEVEL_FIVE: case CORE_LEVEL_SIX: case CORE_LEVEL_SEVEN: case CORE_LEVEL_EIGHT: case CORE_LEVEL_NINE: case CORE_LEVEL_TEN: case CORE_LEVEL_ELEVEN: case CORE_LEVEL_TWELVE: case CORE_LEVEL_THIRTEEN: case CORE_LEVEL_FOURTEEN: case CORE_LEVEL_FIFTEEN: // Processors with compute units disable all cores in an entire compute unit at a time // For example, on a processor with two cores per compute unit, the effective // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and // CORE_LEVEL_EIGHT. RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3; LeveledCores = RequestedCores; LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; LeveledCores = (LeveledCores <= TotalEnabledCoresOnNode) ? LeveledCores : TotalEnabledCoresOnNode; if (LeveledCores != 1) { LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; } if (LeveledCores != RequestedCores) { PutEventLog ( AGESA_WARNING, CPU_WARNING_ADJUSTED_LEVELING_MODE, RequestedCores, LeveledCores, 0, 0, StdHeader ); } break; default: ASSERT (FALSE); } // Set down core register GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, 0, (CONST VOID **)&FamilySpecificServices, StdHeader); if (FamilySpecificServices != NULL) { IDS_HDT_CONSOLE (CPU_TRACE, " SetDownCoreRegister: LeveledCores %d CoreLevelMode %d\n", LeveledCores, CoreLevelMode); RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &SocketAndModule, &SocketAndModule, &LeveledCores, CoreLevelMode, StdHeader); // If the down core register is updated, trigger a warm reset. if (RegUpdated) { GetWarmResetFlag (StdHeader, &Request); Request.RequestBit = TRUE; Request.StateBits = Request.PostStage - 1; IDS_HDT_CONSOLE (CPU_TRACE, " Request a warm reset.\n"); SetWarmResetFlag (StdHeader, &Request); } } return (AGESA_SUCCESS); }
/** * Should message-based C1e be enabled * * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval TRUE Message-based C1e is supported. * @retval FALSE Message-based C1e cannot be enabled. * */ BOOLEAN STATIC IsMsgBasedC1eFeatureEnabled ( IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINTN Link; UINTN LinkCount; UINT32 Socket; UINT32 Module; BOOLEAN IsEnabled; PCI_ADDR PciAddress; AGESA_STATUS AgesaStatus; HT_HOST_FEATS HtHostFeats; CPU_SPECIFIC_SERVICES *CpuServices; MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; ASSERT (PlatformConfig->C1eMode < MaxC1eMode); IsEnabled = FALSE; if (PlatformConfig->C1eMode == C1eModeMsgBased) { ASSERT (PlatformConfig->C1ePlatformData < 0x10000); ASSERT (PlatformConfig->C1ePlatformData != 0); if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) { IsEnabled = TRUE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) { IsEnabled = FALSE; break; } else { // If the CPU revision supports message-based C1e, check whether the feature should // be disabled based on the speed of ncHT links (HT1). GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader); for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { HtHostFeats.HtHostValue = 0; for (LinkCount = 0; LinkCount < 8; LinkCount++) { if (FindHtHostCapability (LinkCount, &PciAddress, StdHeader)) { CpuServices->GetHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader); if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) { IsEnabled = FALSE; break; } } } } // Exit for (Module = 0; Module < GetPlatformNumberOfModules; Module++) if (!IsEnabled) { break; } } } } // Exit for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) if (!IsEnabled) { break; } } } } return IsEnabled; }
/** * Enable L3 dependent features. * * L3 features initialization requires the following series of steps. * 1. Disable L3 and DRAM scrubbers on all nodes * 2. Wait 40us for outstanding scrub results to complete * 3. Disable all cache activity in the system * 4. Issue WBINVD on all active cores * 5. Initialize Probe Filter, if supported * 6. Initialize ATM Mode, if supported * 7. Enable all cache activity in the system * 8. Restore L3 and DRAM scrubber register values * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval AGESA_SUCCESS Always succeeds. * */ AGESA_STATUS STATIC InitializeL3Feature ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 CpuCount; UINT32 Socket; BOOLEAN HtAssistEnabled; BOOLEAN AtmModeEnabled; AGESA_STATUS AgesaStatus; AP_MAILBOXES ApMailboxes; AP_EXE_PARAMS ApParams; UINT32 Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE]; L3_FEATURE_FAMILY_SERVICES *FamilyServices[MAX_SOCKETS_SUPPORTED]; AgesaStatus = AGESA_SUCCESS; HtAssistEnabled = TRUE; AtmModeEnabled = TRUE; IDS_HDT_CONSOLE (CPU_TRACE, " Enabling L3 dependent features\n"); // There are many family service call outs. Initialize the family service array while // cache is still enabled. for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (const VOID **) &FamilyServices[Socket], StdHeader); } else { FamilyServices[Socket] = NULL; } } if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) { // Check for optimal settings GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); CpuCount = GetNumberOfProcessors (StdHeader); if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) || ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { // Only check for non-optimal HT Assist setting is if's supported. if ((FamilyServices[Socket] != NULL) && (FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader))) { if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) { // Non-optimal settings. Log an event. AgesaStatus = AGESA_WARNING; PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader); break; } } } } } else { // Disable the scrubbers. for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (FamilyServices[Socket] != NULL) { FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); // If any node in the system does not support Probe Filter, disable it on the system if (!FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { HtAssistEnabled = FALSE; } // If any node in the system does not support ATM mode, disable it on the system if (!FamilyServices[Socket]->IsAtmModeSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { AtmModeEnabled = FALSE; } } } // Wait for 40us WaitMicroseconds ((UINT32) 40, StdHeader); // Run DisableAllCaches on AP cores. ApParams.StdHeader = *StdHeader; ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE; ApParams.RelatedDataBlock = (VOID *) &HtAssistEnabled; ApParams.RelatedBlockLength = sizeof (BOOLEAN); RunLateApTaskOnAllAPs (&ApParams, StdHeader); // Run DisableAllCaches on core 0. DisableAllCaches (&ApParams); // Family hook before initialization. for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (FamilyServices[Socket] != NULL) { FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader); } } // Activate Probe Filter & ATM mode. for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (FamilyServices[Socket] != NULL) { if (HtAssistEnabled) { FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader); } if (AtmModeEnabled) { FamilyServices[Socket]->AtmModeInit (FamilyServices[Socket], Socket, StdHeader); } } } // Family hook after initialization. for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (FamilyServices[Socket] != NULL) { FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader); } } // Run EnableAllCaches on core 0. EnableAllCaches (&ApParams); // Run EnableAllCaches on every core. ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE; RunLateApTaskOnAllAPs (&ApParams, StdHeader); // Restore the scrubbers. for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (FamilyServices[Socket] != NULL) { FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); } } } return AgesaStatus; }
/** * Enable the C6 C-state * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @retval AGESA_SUCCESS Always succeeds. * */ AGESA_STATUS STATIC InitializeC6Feature ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 BscSocket; UINT32 Ignored; UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; UINT32 NumberOfCores; AP_TASK TaskPtr; AMD_CPU_EARLY_PARAMS CpuEarlyParams; C6_FAMILY_SERVICES *C6FamilyServices; AGESA_STATUS IgnoredSts; CpuEarlyParams.PlatformConfig = *PlatformConfig; TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket; TaskPtr.DataTransfer.DataSizeInDwords = 2; TaskPtr.DataTransfer.DataPtr = &EntryPoint; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = PASS_EARLY_PARAMS; OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); if (((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) && !(IsSecureS3 (StdHeader))) { // Load any required microcode patches on both normal boot and resume from S3. IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader); if (C6FamilyServices != NULL) { C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader); } // run code on all APs TaskPtr.DataTransfer.DataSizeInDwords = 0; TaskPtr.ExeFlags = 0; NumberOfSockets = GetPlatformNumberOfSockets (); for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader); if (C6FamilyServices != NULL) { // run code on all APs TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit; if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { if ((Socket != BscSocket) || (Core != BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } } } } } } return AGESA_SUCCESS; }
/** * Save and Restore or Initialize the content of the mailbox registers. * * The registers used for AP mailbox should have the content related to their function * preserved. * * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. * * @return AGESA_SUCCESS Always succeeds. * */ AGESA_STATUS STATIC PreserveMailboxes ( IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices; UINT32 Socket; UINT32 Module; PCI_ADDR BaseAddress; PCI_ADDR MailboxRegister; PCI_ADDR *NextRegister; AGESA_STATUS IgnoredStatus; AGESA_STATUS HeapStatus; UINT32 Value; ALLOCATE_HEAP_PARAMS AllocateParams; LOCATE_HEAP_PTR LocateParams; UINT32 RegisterEntryIndex; BaseAddress.AddressValue = ILLEGAL_SBDFO; if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) { // The save step. Save either the register content or zero (for cold boot, if family specifies that). AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES))); AllocateParams.Persist = HEAP_SYSTEM_MEM; HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader); ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL)); LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader); RegisterEntryIndex = 0; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL); NextRegister = FamilySpecificServices->RegisterList; while (NextRegister->AddressValue != ILLEGAL_SBDFO) { ASSERT (RegisterEntryIndex < (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) { Value = 0; } else { MailboxRegister = BaseAddress; MailboxRegister.Address.Function = NextRegister->Address.Function; MailboxRegister.Address.Register = NextRegister->Address.Register; LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); } (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value; RegisterEntryIndex++; NextRegister++; } } } } } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) { // The restore step. Just write out the saved content in the buffer. LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader); ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL)); RegisterEntryIndex = 0; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); NextRegister = FamilySpecificServices->RegisterList; while (NextRegister->AddressValue != ILLEGAL_SBDFO) { ASSERT (RegisterEntryIndex < (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); MailboxRegister = BaseAddress; MailboxRegister.Address.Function = NextRegister->Address.Function; MailboxRegister.Address.Register = NextRegister->Address.Register; Value = (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex]; LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader); RegisterEntryIndex++; NextRegister++; } } } } HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader); } return AGESA_SUCCESS; }