/* XXX: This is copied in large part from AddAllRats above; for
* maintainability, AddAllRats probably wants to be tweaked to use this
* version of the code so that we don't have duplication. */
NetListListType
CollectSubnets (bool SelectedOnly)
{
NetListListType result = { 0, 0, NULL };
NetListTypePtr Nets, Wantlist;
NetTypePtr lonesome;
ConnectionTypePtr onepin;
/* the netlist library has the text form
* ProcNetlist fills in the Netlist
* structure the way the final routing
* is supposed to look
*/
Wantlist = ProcNetlist (&PCB->NetlistLib);
if (!Wantlist)
{
Message (_("Can't add rat lines because no netlist is loaded.\n"));
return result;
}
/* initialize finding engine */
InitConnectionLookup ();
SaveFindFlag (DRCFLAG);
/* now we build another netlist (Nets) for each
* net in Wantlist that shows how it actually looks now,
* then fill in any missing connections with rat lines.
*
* we first assume each connection is separate
* (no routing), then gather them into groups
* if the net is all routed, the new netlist (Nets)
* will have only one net entry.
* Note that DrawShortestRats consumes all nets
* from Nets, so *Nets is empty after the
* DrawShortestRats call
*/
NET_LOOP (Wantlist);
{
Nets = GetNetListMemory (&result);
CONNECTION_LOOP (net);
{
if (!SelectedOnly
|| TEST_FLAG (SELECTEDFLAG, (PinTypePtr) connection->ptr2))
{
lonesome = GetNetMemory (Nets);
onepin = GetConnectionMemory (lonesome);
*onepin = *connection;
lonesome->Style = net->Style;
}
}
END_LOOP;
/* Note that AndRats is *FALSE* here! */
GatherSubnets (Nets, SelectedOnly, false);
}
END_LOOP;
FreeConnectionLookupMemory ();
RestoreFindFlag ();
return result;
}
/*!
* \brief AddAllRats puts the rats nest into the layout from the loaded
* netlist.
*
* If SelectedOnly is true, it will only draw rats to selected pins and
* pads.
*/
bool
AddAllRats (bool SelectedOnly, void (*funcp) (register ConnectionType *, register ConnectionType *, register RouteStyleType *))
{
NetListType *Nets, *Wantlist;
NetType *lonesome;
ConnectionType *onepin;
bool changed, Warned = false;
/* the netlist library has the text form
* ProcNetlist fills in the Netlist
* structure the way the final routing
* is supposed to look
*/
Wantlist = ProcNetlist (&PCB->NetlistLib);
if (!Wantlist)
{
Message (_("Can't add rat lines because no netlist is loaded.\n"));
return (false);
}
changed = false;
/* initialize finding engine */
InitConnectionLookup ();
Nets = (NetListType *)calloc (1, sizeof (NetListType));
/* now we build another netlist (Nets) for each
* net in Wantlist that shows how it actually looks now,
* then fill in any missing connections with rat lines.
*
* we first assume each connection is separate
* (no routing), then gather them into groups
* if the net is all routed, the new netlist (Nets)
* will have only one net entry.
* Note that DrawShortestRats consumes all nets
* from Nets, so *Nets is empty after the
* DrawShortestRats call
*/
NET_LOOP (Wantlist);
{
CONNECTION_LOOP (net);
{
if (!SelectedOnly
|| TEST_FLAG (SELECTEDFLAG, (PinType *) connection->ptr2))
{
lonesome = GetNetMemory (Nets);
onepin = GetConnectionMemory (lonesome);
*onepin = *connection;
lonesome->Style = net->Style;
}
}
END_LOOP;
Warned |= GatherSubnets (Nets, SelectedOnly, true);
if (Nets->NetN > 0)
changed |= DrawShortestRats (Nets, funcp);
}
END_LOOP;
FreeNetListMemory (Nets);
free (Nets);
FreeConnectionLookupMemory ();
if (funcp)
return (true);
if (Warned || changed)
Draw ();
if (Warned)
Settings.RatWarn = true;
if (changed)
{
IncrementUndoSerialNumber ();
if (PCB->Data->RatN > 0)
{
Message ("%d rat line%s remaining\n", PCB->Data->RatN,
PCB->Data->RatN > 1 ? "s" : "");
}
return (true);
}
if (!SelectedOnly && !Warned)
{
if (!PCB->Data->RatN && !badnet)
Message (_("Congratulations!!\n"
"The layout is complete and has no shorted nets.\n"));
else
Message (_("Nothing more to add, but there are\n"
"either rat-lines in the layout, disabled nets\n"
"in the net-list, or missing components\n"));
}
return (false);
}
/*!
* \brief Read the library-netlist build a true Netlist structure.
*/
NetListType *
ProcNetlist (LibraryType *net_menu)
{
ConnectionType *connection;
ConnectionType LastPoint;
NetType *net;
static NetListType *Wantlist = NULL;
if (!net_menu->MenuN)
return (NULL);
FreeNetListMemory (Wantlist);
free (Wantlist);
badnet = false;
/* find layer groups of the component side and solder side */
bottom_group = GetLayerGroupNumberBySide (BOTTOM_SIDE);
top_group = GetLayerGroupNumberBySide (TOP_SIDE);
Wantlist = (NetListType *)calloc (1, sizeof (NetListType));
if (Wantlist)
{
ALLPIN_LOOP (PCB->Data);
{
pin->Spare = NULL;
CLEAR_FLAG (DRCFLAG, pin);
}
ENDALL_LOOP;
ALLPAD_LOOP (PCB->Data);
{
pad->Spare = NULL;
CLEAR_FLAG (DRCFLAG, pad);
}
ENDALL_LOOP;
MENU_LOOP (net_menu);
{
if (menu->Name[0] == '*' || menu->flag == 0)
{
badnet = true;
continue;
}
net = GetNetMemory (Wantlist);
if (menu->Style)
{
STYLE_LOOP (PCB);
{
if (style->Name && !NSTRCMP (style->Name, menu->Style))
{
net->Style = style;
break;
}
}
END_LOOP;
}
else /* default to NULL if none found */
net->Style = NULL;
ENTRY_LOOP (menu);
{
if (SeekPad (entry, &LastPoint, false))
{
if (TEST_FLAG (DRCFLAG, (PinType *) LastPoint.ptr2))
Message (_
("Error! Element %s pin %s appears multiple times in the netlist file.\n"),
NAMEONPCB_NAME ((ElementType *) LastPoint.ptr1),
(LastPoint.type ==
PIN_TYPE) ? ((PinType *) LastPoint.ptr2)->
Number : ((PadType *) LastPoint.ptr2)->Number);
else
{
connection = GetConnectionMemory (net);
*connection = LastPoint;
/* indicate expect net */
connection->menu = menu;
/* mark as visited */
SET_FLAG (DRCFLAG, (PinType *) LastPoint.ptr2);
if (LastPoint.type == PIN_TYPE)
((PinType *) LastPoint.ptr2)->Spare = (void *) menu;
else
((PadType *) LastPoint.ptr2)->Spare = (void *) menu;
}
}
else
badnet = true;
/* check for more pins with the same number */
for (; SeekPad (entry, &LastPoint, true);)
{
connection = GetConnectionMemory (net);
*connection = LastPoint;
/* indicate expect net */
connection->menu = menu;
/* mark as visited */
SET_FLAG (DRCFLAG, (PinType *) LastPoint.ptr2);
if (LastPoint.type == PIN_TYPE)
((PinType *) LastPoint.ptr2)->Spare = (void *) menu;
else
((PadType *) LastPoint.ptr2)->Spare = (void *) menu;
}
}
END_LOOP;
}
END_LOOP;
}
/* clear all visit marks */
ALLPIN_LOOP (PCB->Data);
{
CLEAR_FLAG (DRCFLAG, pin);
}
ENDALL_LOOP;
ALLPAD_LOOP (PCB->Data);
{
CLEAR_FLAG (DRCFLAG, pad);
}
ENDALL_LOOP;
return (Wantlist);
}
