AGESA_STATUS
GfxInitAtPost (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_POST_PARAMS *PostParamsPtr;
GFX_CARD_CARD_INFO GfxDiscreteCardInfo;
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Enter\n");
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
if (GfxLibIsControllerPresent (StdHeader)) {
if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader);
GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader);
if (GfxDiscreteCardInfo.PciGfxCardBitmap != 0 ||
(GfxDiscreteCardInfo.AmdPcieGfxCardBitmap & GfxDiscreteCardInfo.PcieGfxCardBitmap) !=
GfxDiscreteCardInfo.AmdPcieGfxCardBitmap) {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n");
}
}
} else {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
Gfx->GfxFusedOff = TRUE;
}
} else {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Exit [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
GfxConfigEnvInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_ENV_PARAMS *EnvParamsPtr;
GFX_PLATFORM_CONFIG *Gfx;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n");
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex;
Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum;
Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate;
Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe;
Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl;
Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon;
Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe;
Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay;
Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon;
Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl;
Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq;
Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue;
Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode;
Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum;
GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader);
}
GNB_DEBUG_CODE (
GfxConfigDebugDump (Gfx);
);
VOID
STATIC
GnbCgttOverrideTN (
IN UINT32 Property,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CGINDx0_Value;
UINT32 CGINDx1_Value;
GFX_PLATFORM_CONFIG *Gfx;
AGESA_STATUS Status;
D0F0x64_x23_STRUCT D0F0x64_x23;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Enter\n");
CGINDx0_Value = 0xFFFFFFFF;
//When orb clock gating is enabled in the BIOS clear CG_ORB_cgtt_lclk_override - bit 13
CGINDx1_Value = 0xFFFFFFFF;
if ((Property & TABLE_PROPERTY_ORB_CLK_GATING) == TABLE_PROPERTY_ORB_CLK_GATING) {
CGINDx1_Value &= 0xFFFFDFFF;
}
//When ioc clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 15
if ((Property & TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) == TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) {
CGINDx1_Value &= 0xFFFF7FFF;
if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) != TABLE_PROPERTY_IOMMU_DISABLED) {
//only IOMMU enabled and IOC clock gating enable
GnbRegisterReadTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, 0, StdHeader);
D0F0x64_x23.Field.SoftOverrideClk0 = 1;
D0F0x64_x23.Field.SoftOverrideClk1 = 1;
D0F0x64_x23.Field.SoftOverrideClk3 = 1;
D0F0x64_x23.Field.SoftOverrideClk4 = 1;
GnbRegisterWriteTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
}
//When smu sclk clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 18
if ((Property & TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) == TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) {
CGINDx1_Value &= 0xFFFBFFFF;
}
Status = GfxLocateConfigData (StdHeader, &Gfx);
if (Status != AGESA_FATAL) {
if (Gfx->GmcClockGating) {
//In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
// CGINDx0, clear bit 27, bit 28
CGINDx0_Value &= 0xE7FFFFFF;
GnbRegisterWriteTN (TYPE_CGIND, 0x0, &CGINDx0_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
// CGINDx1, clear bit 11
CGINDx1_Value &= 0xFFFFF7FF;
}
}
if (CGINDx1_Value != 0xFFFFFFFF) {
GnbRegisterWriteTN (TYPE_CGIND, 0x1, &CGINDx1_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Exit\n");
}
AGESA_STATUS
GfxPostInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_POST_PARAMS *PostParamsPtr;
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
D0F0xBC_xC00C0000_STRUCT D0F0xBC_xC00C0000;
D0F0xD4_x013014AC_STRUCT D0F0xD4_x13014AC;
D0F0xD4_x013014B6_STRUCT D0F0xD4_x13014B6;
GNB_HANDLE *GnbHandle;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
ASSERT (GnbHandle != NULL);
GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C0000_TYPE,
D0F0xBC_xC00C0000_ADDRESS, &D0F0xBC_xC00C0000.Value, 0, StdHeader);
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
if (D0F0xBC_xC00C0000.Field.GPU_DIS == 1) {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
Gfx->GfxFusedOff = TRUE;
}
} else {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
}
if (PostParamsPtr->MemConfig.UmaMode == UMA_NONE) {
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014AC_TYPE, D0F0xD4_x013014AC_ADDRESS, &D0F0xD4_x13014AC.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014B6_TYPE, D0F0xD4_x013014B6_ADDRESS, &D0F0xD4_x13014B6.Value, 0, StdHeader);
D0F0xD4_x13014AC.Field.StrapBifAudioEnPin = FALSE;
D0F0xD4_x13014B6.Field.StrapBifAudioEn = FALSE;
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014AC_TYPE, D0F0xD4_x013014AC_ADDRESS, &D0F0xD4_x13014AC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014B6_TYPE, D0F0xD4_x013014B6_ADDRESS, &D0F0xD4_x13014B6.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
if (D0F0xBC_xC00C0000.Field.GPU_DIS != 1) {
// Power down iGPU
GfxRequestGPUPowerV3 (Gfx, 0);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceML Exit [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
GfxMidInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_FATAL) {
GfxFmDisableController (StdHeader);
} else {
if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
Status = GfxEnableGmmAccess (Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status != AGESA_SUCCESS) {
// Can not initialize GMM registers going to disable GFX controller
IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n");
Gfx->UmaInfo.UmaMode = UMA_NONE;
GfxFmDisableController (StdHeader);
} else {
Status = GfxGmcInitTN (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxSetBootUpVoltageTN (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxInitSsid (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxIntegratedEnumerateAudioConnectors (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
exec803 /* GfxAzWorkaroundTN */ (Gfx);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxConfigMidInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_MID_PARAMS *MidParamsPtr;
GFX_PLATFORM_CONFIG *Gfx;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Enter\n");
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
Gfx->iGpuVgaMode = MidParamsPtr->GnbMidConfiguration.iGpuVgaMode;
}
GNB_DEBUG_CODE (
GfxConfigDebugDump (Gfx);
);
/**
* Build integrated info table
* GMC FB access requred
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntInfoTableInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
if (GfxLibIsControllerPresent (StdHeader)) {
Status = GfxLocateConfigData (StdHeader, &Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status != AGESA_FATAL) {
Status = GfxIntInfoTableInitTN (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxInitAtEnvPost (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Enter\n");
Status = GfxLocateConfigData (StdHeader, &Gfx);
if (Status == AGESA_SUCCESS) {
if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
Status = GfxStrapsInit (Gfx);
ASSERT (Status == AGESA_SUCCESS);
} else {
GfxDisableController (StdHeader);
}
} else {
GfxDisableController (StdHeader);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Exit [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
PcieFmAlibBuildAcpiTable (
IN VOID *AlibSsdtPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
UINT32 AmlObjName;
GFX_PLATFORM_CONFIG *Gfx;
VOID *AmlObjPtr;
BOOLEAN AltVddNbSupport;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n");
AgesaStatus = AGESA_SUCCESS;
AltVddNbSupport = TRUE;
// AmlObjName = 'A0DA';
AmlObjName = 0x41304441;
AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
Status = GfxLocateConfigData (StdHeader, &Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
if ((Status != AGESA_SUCCESS) || (GnbBuildOptions.CfgAltVddNb == FALSE) || (Gfx->UmaInfo.MemClock > DDR1333_FREQUENCY) ||
((Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != 0) && GfxLibIsControllerPresent (StdHeader))) {
AltVddNbSupport = FALSE;
}
// CBS/IDS can change AltVddNbSupport
IDS_OPTION_HOOK (IDS_GNB_ALTVDDNB, &AltVddNbSupport, StdHeader);
if (!AltVddNbSupport) {
IDS_HDT_CONSOLE (GNB_TRACE, " AltVddNb - Disabled\n");
*(UINT8*)((UINT8*) AmlObjPtr + 5) = 0;
}
} else {
AgesaStatus = AGESA_ERROR;
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxInitSview (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
UINT32 OriginalCmdReg;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
if (GfxLibIsControllerPresent (StdHeader)) {
if (!GfxFmIsVbiosPosted (Gfx)) {
GFX_VBIOS_IMAGE_INFO VbiosImageInfo;
LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
VbiosImageInfo.ImagePtr = NULL;
VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress;
VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST;
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, &OriginalCmdReg, StdHeader);
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader);
Status = AgesaGetVbiosImage (0, &VbiosImageInfo);
if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) {
GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx);
} else {
GfxFmDisableController (StdHeader);
AgesaStatus = AGESA_ERROR;
}
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0x00, OriginalCmdReg, StdHeader);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxConfigEnvInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_ENV_PARAMS *EnvParamsPtr;
GFX_PLATFORM_CONFIG *Gfx;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n");
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
EnvParamsPtr = (AMD_ENV_PARAMS *)StdHeader;
Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex;
Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum;
Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate;
Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value;
Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum;
GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader);
}
GNB_DEBUG_CODE (
GfxConfigDebugDump (Gfx);
);
AGESA_STATUS
GfxMidInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
UINT8 AudioEPCount;
GMMx5F50_STRUCT GMMx5F50;
AMD_MID_PARAMS *MidParamsPtr;
UINT8 MaxAudioEndpoints;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_FATAL) {
GfxFmDisableController (StdHeader);
} else {
if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
Status = GfxEnableGmmAccessV3 (Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status != AGESA_SUCCESS) {
// Can not initialize GMM registers going to disable GFX controller
IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n");
Gfx->UmaInfo.UmaMode = UMA_NONE;
GfxFmDisableController (StdHeader);
} else {
MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
MaxAudioEndpoints = MidParamsPtr->GnbMidConfiguration.MaxNumAudioEndpoints;
Status = GfxGmcInitML (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxSamuInit (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxInitSsid (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
AudioEPCount = 0;
Status = GfxIntAudioEPEnumV3 (Gfx, &AudioEPCount);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (AudioEPCount > MaxAudioEndpoints) {
AudioEPCount = MaxAudioEndpoints;
}
if (AudioEPCount > GnbBuildOptionsML.GnbCommonOptions.CfgGnbNumDisplayStreamPipes) {
AudioEPCount = GnbBuildOptionsML.GnbCommonOptions.CfgGnbNumDisplayStreamPipes;
}
AudioEPCount = 7 - AudioEPCount;
GnbRegisterReadML (GnbGetHandle (StdHeader), GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, 0, StdHeader);
GMMx5F50.Field.PORT_CONNECTIVITY = AudioEPCount;
GMMx5F50.Field.PORT_CONNECTIVITY_OVERRIDE_ENABLE = 1;
GnbRegisterWriteML (GnbGetHandle (StdHeader), GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}