AGESA_STATUS
GfxEnableGmmAccessV5 (
IN OUT GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 Value;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
ASSERT (GnbHandle != NULL);
// GmmBase should be 0 before enable.
ASSERT (GnbHandle->GmmBase == 0);
if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for GMM allocated by reading D1F0x24 Graphics Memory Mapped Base Address
Gfx->GmmBase = 0;
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x24, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
Gfx->GmmBase |= (Value & 0xfffffff0);
if (Gfx->GmmBase == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for FB allocated
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
if ((Value & 0xfffffff0) == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
//Push CPU MMIO pci config to S3 script
GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
// Turn on memory decoding on GFX to enable access to GMM register space
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
//Push iGPU pci config to S3 script
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
GnbHandle->GmmBase = Gfx->GmmBase;
return AGESA_SUCCESS;
}
AGESA_STATUS
GfxEnableGmmAccess (
IN OUT GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 Value;
if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for GMM allocated
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx));
if (Gfx->GmmBase == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for FB allocated
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
if ((Value & 0xfffffff0) == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
//Push CPU MMIO pci config to S3 script
GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
// Turn on memory decoding on APC to enable access to GMM register space
if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
//Push APC pci config to S3 script
GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
}
// Turn on memory decoding on GFX to enable access to GMM register space
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
//Push iGPU pci config to S3 script
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
return AGESA_SUCCESS;
}