/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Check if an injected conversion is ready */
if (hadc->State == HAL_ADC_STATE_EOC_INJ) {
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
} else {
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_REG;
}
HAL_ADC_ConvCpltCallback(hadc);
}
/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
{
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
(hadc->Init.ContinuousConvMode == DISABLE) &&
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
}
else
{
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
/**
* @brief Handles ADC interrupt request
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
{
uint32_t tmp1 = 0, tmp2 = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
/* Check End of conversion flag for regular channels */
if(tmp1 && tmp2)
{
/* Check if an injected conversion is ready */
if(hadc->State == HAL_ADC_STATE_EOC_INJ)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_REG;
}
if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
{
if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
/* DISABLE the ADC end of conversion interrupt for regular group */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* DISABLE the ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
}
else
{
if (hadc->NbrOfCurrentConversionRank == 0)
{
hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
}
/* Decrement the number of conversion when an interrupt occurs */
hadc->NbrOfCurrentConversionRank--;
/* Check if all conversions are finished */
if(hadc->NbrOfCurrentConversionRank == 0)
{
/* DISABLE the ADC end of conversion interrupt for regular group */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
/* DISABLE the ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
}
}
}
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
/* Clear the ADCx flag for regular end of conversion */
__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
/* Check End of conversion flag for injected channels */
if(tmp1 && tmp2)
{
/* Check if a regular conversion is ready */
if(hadc->State == HAL_ADC_STATE_EOC_REG)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_EOC_INJ;
}
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)
{
/* DISABLE the ADC end of conversion interrupt for injected group */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
}
/* Conversion complete callback */
HAL_ADCEx_InjectedConvCpltCallback(hadc);
/* Clear the ADCx flag for injected end of conversion */
__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
/* Check Analog watchdog flag */
if(tmp1 && tmp2)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_AWD;
/* Clear the ADCx's Analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
/* Level out of window callback */
HAL_ADC_LevelOutOfWindowCallback(hadc);
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
/* Check Overrun flag */
if(tmp1 && tmp2)
{
/* Change ADC state to overrun state */
hadc->State = HAL_ADC_STATE_ERROR;
/* Set ADC error code to overrun */
hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
/* Error callback */
HAL_ADC_ErrorCallback(hadc);
}
}