/***********************************************************************************
* @fn main
*
* @brief This is the main entry of the "Light Switch" application.
* After the application modes are chosen the switch can
* send toggle commands to a light device.
*
* @param basicRfConfig - file scope variable. Basic RF configuration
* data
* appState - file scope variable. Holds application state
*
* @return none
*/
void main(void)
{
uint8 appMode = NONE;
// Config basicRF
basicRfConfig.panId = PAN_ID;
basicRfConfig.channel = RF_CHANNEL;
basicRfConfig.ackRequest = TRUE;
#ifdef SECURITY_CCM
basicRfConfig.securityKey = key;
#endif
// Initalise board peripherals
halBoardInit();
// halJoystickInit();
// Initalise hal_rf
if(halRfInit()==FAILED) {
HAL_ASSERT(FALSE);
}
// Indicate that device is powered
halLedSet(2);//*****************by boo LED2(P1_1=1)
halLedClear(1);//***************by boo LED1(P1_0=0)
/************Select one and shield to another***********by boo*/
appSwitch(); //½ÚµãΪ°´¼üS1 P0_4
// Role is undefined. This code should not be reached
HAL_ASSERT(FALSE);
}
/**************************************************************************************************
* @fn osal_mem_init
*
* @brief This function is the OSAL heap memory management initialization callback.
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
*/
void osal_mem_init(void)
{
HAL_ASSERT(((OSALMEM_MIN_BLKSZ % OSALMEM_HDRSZ) == 0));
HAL_ASSERT(((OSALMEM_LL_BLKSZ % OSALMEM_HDRSZ) == 0));
HAL_ASSERT(((OSALMEM_SMALL_BLKSZ % OSALMEM_HDRSZ) == 0));
#if OSALMEM_PROFILER
(void)osal_memset(theHeap, OSALMEM_INIT, MAXMEMHEAP);
#endif
// Setup a NULL block at the end of the heap for fast comparisons with zero.
theHeap[OSALMEM_LASTBLK_IDX].val = 0;
// Setup the small-block bucket.
ff1 = theHeap;
ff1->val = OSALMEM_SMALLBLK_BUCKET; // Set 'len' & clear 'inUse' field.
// Set 'len' & 'inUse' fields - this is a 'zero data bytes' lifetime allocation to block the
// small-block bucket from ever being coalesced with the wilderness.
theHeap[OSALMEM_SMALLBLK_HDRCNT].val = (OSALMEM_HDRSZ | OSALMEM_IN_USE);
// Setup the wilderness.
theHeap[OSALMEM_BIGBLK_IDX].val = OSALMEM_BIGBLK_SZ; // Set 'len' & clear 'inUse' field.
#if ( OSALMEM_METRICS )
/* Start with the small-block bucket and the wilderness - don't count the
* end-of-heap NULL block nor the end-of-small-block NULL block.
*/
blkCnt = blkFree = 2;
#endif
}
// =============================================================================
// hal_PwlOutputDisable
// -----------------------------------------------------------------------------
/// Disables the output of the selected Pwl (forced to 0), or reenable it.
/// @param disable If \c TRUE, the output is disabled,
/// if \c FALSE, the output returns to its normal behaviour.
// =============================================================================
PUBLIC VOID hal_PwlOutputDisable(HAL_PWL_ID_T id, BOOL disable)
{
if (HAL_PWL_NONE == id)
{
return;
}
// check glowing
HAL_ASSERT(g_halCfg->pwmCfg.pwlGlowPosition != id, "hal_PwlOutputDisable: PWL Id (%d) is configured as Glowing", id);
// is ID valid ?
HAL_ASSERT((HAL_PWL_0 == id) || (HAL_PWL_1 == id), "hal_PwlOutputDisable: Invalid PWL Id (%d)",id);
// PWL 1 and not inverted or PWL 0 and inverted
if ( (HAL_PWL_1 == g_halCfg->pwmCfg.pwlGlowPosition) != (HAL_PWL_1 == id))
{
if (disable)
{
hwp_pwm->PWL1_Config = PWM_PWL1_CLR_OE;
}
else
{
hwp_pwm->PWL1_Config = PWM_PWL1_SET_OE;
}
}
else
{
if (disable)
{
hwp_pwm->PWL0_Config = PWM_PWL0_CLR_OE;
}
else
{
hwp_pwm->PWL0_Config = PWM_PWL0_SET_OE;
}
}
}
// =============================================================================
// hal_IfcTransferStart
// -----------------------------------------------------------------------------
/// Start an IFC transfer
///
/// This is a non blocking function that starts the transfer
/// and returns the hand.
///
/// @param requestId Describe the direction of the tranfer (rx or
/// tx) and the module to or from which data are to be moved.
/// @param memStartAddr. Start address of the buffer where data
/// to be sent are located or where to put the data read, according
/// to the request defined by the previous parameter
/// @param xferSize Number of bytes to transfer. The maximum size
/// is 2^20 - 1 bytes.
/// @param ifcMode Mode of the transfer (Autodisable or not, 8 or 32 bits)
/// @return Channel got or HAL_UNKNOWN_CHANNEL.
// =============================================================================
PROTECTED UINT8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, UINT8* memStartAddr, UINT32 xferSize, HAL_IFC_MODE_T ifcMode)
{
// Check buffer alignment depending on the mode
if (ifcMode != HAL_IFC_SIZE_8_MODE_MANUAL && ifcMode != HAL_IFC_SIZE_8_MODE_AUTO)
{
// Then ifcMode == HAL_IFC_SIZE_32, check word alignment
HAL_ASSERT(((UINT32)memStartAddr%4) == 0,
"HAL IFC: 32 bits transfer misaligned 0x@%08X", memStartAddr);
}
else
{
// ifcMode == HAL_IFC_SIZE_8, nothing to check
}
HAL_ASSERT(xferSize < (1<<SYS_IFC_TC_LEN),
"HAL IFC: Transfer size too large: %d", xferSize);
UINT32 status = hal_SysEnterCriticalSection();
UINT8 channel;
UINT8 i;
// Check the requested id is not currently already used.
for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++)
{
if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control, SYS_IFC_REQ_SRC) == requestId)
{
// This channel is or was used for the requestId request.
// Check it is still in use.
HAL_ASSERT((hwp_sysIfc->std_ch[i].status & SYS_IFC_ENABLE) == 0,
"HAL: Attempt to use the IFC to deal with a %d"
" request still active on channel %d", requestId, i);
}
}
channel = SYS_IFC_CH_TO_USE(hwp_sysIfc->get_ch) ;
if (channel >= SYS_IFC_STD_CHAN_NB)
{
hal_SysExitCriticalSection(status);
return HAL_UNKNOWN_CHANNEL;
}
g_halModuleIfcChannelOwner[channel] = requestId;
hwp_sysIfc->std_ch[channel].start_addr = (UINT32) memStartAddr;
hwp_sysIfc->std_ch[channel].tc = xferSize;
hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId)
| ifcMode
#if (CHIP_HAS_ASYNC_TCU)
| SYS_IFC_CH_RD_HW_EXCH
#endif
| SYS_IFC_ENABLE);
hal_SysExitCriticalSection(status);
return channel;
}
/***************************************************************************//**
* TMR_reload()
* See "core_timer.h" for details of how to use this function.
*/
void TMR_reload
(
timer_instance_t * this_timer,
uint32_t load_value
)
{
HAL_ASSERT( this_timer != NULL_timer_instance )
HAL_ASSERT( load_value != 0 )
HAL_set_32bit_reg(this_timer->base_address, TimerLoad, load_value );
}
// =============================================================================
// hal_PwlSelLevel
// -----------------------------------------------------------------------------
/// Set the average on time for the selected PWL output
/// Thus, the integrated output represents a certain luminosity level
///
/// @param level The average on-time can be set via this value. A value of
/// 0 will force the PWL output to 0 while a value of 0xff will force the
/// value to 1. All intermediate values will generate an average duty cycle
/// of (level/255 * 100)
// =============================================================================
PUBLIC VOID hal_PwlSelLevel(HAL_PWL_ID_T id, UINT8 level)
{
UINT32 Val;
// Check Param validity
if (HAL_PWL_NONE == id)
{
return;
}
// check glowing
HAL_ASSERT(g_halCfg->pwmCfg.pwlGlowPosition != id, "hal_PwlSelLevel: PWL Id (%d) is configured as Glowing", id);
// is ID valid ?
HAL_ASSERT((HAL_PWL_0 == id) || (HAL_PWL_1 == id), "hal_PwlSelLevel: Invalid PWL Id (%d)",id);
// PWL 1 and not inverted or PWL 0 and inverted
// inverted is glow on PWL_1
// boolean xor is equivalent to != (but only with plain boolean values)
if ( (HAL_PWL_1 == g_halCfg->pwmCfg.pwlGlowPosition) != (HAL_PWL_1 == id))
{
Val = PWM_PWL1_SET_OE; // Always enable
if (level == 0)
{
Val |= PWM_PWL1_FORCE_L;
}
else if (level == 0xff)
{
Val |= PWM_PWL1_FORCE_H;
}
else
{
Val |= (PWM_PWL1_EN_H | PWM_PWL1_THRESHOLD(level));
}
hwp_pwm->PWL1_Config = Val;
}
else
{
Val = PWM_PWL0_SET_OE; // Always enable
if (level == 0)
{
Val |= PWM_PWL0_FORCE_L;
}
else if (level == 0xff)
{
Val |= PWM_PWL0_FORCE_H;
}
else
{
Val |= (PWM_PWL0_EN_H | PWM_PWL_MIN(level));
}
hwp_pwm->PWL0_Config = Val;
}
hal_PwmResourceMgmt();
}
// =============================================================================
// hal_AifStream
// -----------------------------------------------------------------------------
/// Play or record a stream from or to a buffer
/// The buffer start address must be aligned on a 32-bit address, and the size
/// must be a multiple of 32 bytes.
/// @param xfer Describes the buffer and size
/// @param direction Define the direction: PLAY for play, RECORD to record.
// =============================================================================
PRIVATE HAL_ERR_T hal_AifStream(CONST HAL_AIF_STREAM_T* xfer, UINT32 direction)
{
UINT32 irqMask = 0;
if (hal_SysGetRequestFreq(HAL_SYS_FREQ_AIF) == HAL_SYS_FREQ_32K)
{
HAL_ASSERT(FALSE, "AIF Stream when resource not active");
}
if (hwp_bbIfc->ch[direction].status & BB_IFC_ENABLE)
{
return HAL_ERR_RESOURCE_BUSY;
}
// Assert on word alignement
HAL_ASSERT(((UINT32)xfer->startAddress)%4 == 0, "BB IFC transfer start \
address not aligned: 0x%x",((UINT32)xfer->startAddress));
// Size must be a multiple of 32 bytes
HAL_ASSERT((xfer->length)%32 == 0, "BB IFC transfer size not mult. of 32-bits");
hwp_bbIfc->ch[direction].start_addr = (UINT32) xfer->startAddress;
hwp_bbIfc->ch[direction].Fifo_Size = xfer->length;
if (xfer->halfHandler != NULL)
{
g_halAifHandlers[direction].halfHandler = xfer->halfHandler;
irqMask |= BB_IFC_HALF_FIFO;
}
else
{
g_halAifHandlers[direction].halfHandler = NULL;
}
if (xfer->endHandler != NULL)
{
g_halAifHandlers[direction].endHandler = xfer->endHandler;
irqMask |= BB_IFC_END_FIFO;
}
else
{
g_halAifHandlers[direction].endHandler = NULL;
}
hwp_bbIfc->ch[direction].int_mask = irqMask;
hwp_bbIfc->ch[direction].control = BB_IFC_ENABLE;
return HAL_ERR_NO;
}
/*********************************************************************
* @fn osal_mem_free
*
* @brief Implementation of the de-allocator functionality.
*
* @param ptr - pointer to the memory to free.
*
* @return void
*/
void osal_mem_free( void *ptr )
{
osalMemHdr_t *currHdr;
halIntState_t intState;
HAL_ENTER_CRITICAL_SECTION( intState ); // Hold off interrupts.
HAL_ASSERT(((uint8 *)ptr >= (uint8 *)_theHeap) && ((uint8 *)ptr < (uint8 *)_theHeap+MAXMEMHEAP));
currHdr = (osalMemHdr_t *)ptr - 1;
HAL_ASSERT(*currHdr & OSALMEM_IN_USE);
*currHdr &= ~OSALMEM_IN_USE;
#if ( OSALMEM_PROFILER )
{
uint16 size = *currHdr;
uint8 idx;
for ( idx = 0; idx < OSALMEM_PROMAX; idx++ )
{
if ( size <= proCnt[idx] )
{
break;
}
}
proCur[idx]--;
}
#endif
#if ( OSALMEM_METRICS )
memAlo -= *currHdr;
blkFree++;
#endif
if ( ff1 > currHdr )
{
ff1 = currHdr;
}
#if ( OSALMEM_PROFILER )
(void)osal_memset( (uint8 *)currHdr+HDRSZ, OSALMEM_REIN, (*currHdr - HDRSZ) );
#endif
HAL_EXIT_CRITICAL_SECTION( intState ); // Re-enable interrupts.
}
/**************************************************************************************************
* @fn osal_mem_free
*
* @brief This function implements the OSAL dynamic memory de-allocation functionality.
*
* input parameters
*
* @param ptr - A valid pointer (i.e. a pointer returned by osal_mem_alloc()) to the memory to free.
*
* output parameters
*
* None.
*
* @return None.
*/
#ifdef DPRINTF_OSALHEAPTRACE
void osal_mem_free_dbg(void *ptr, const char *fname, unsigned lnum)
#else /* DPRINTF_OSALHEAPTRACE */
void osal_mem_free(void *ptr)
#endif /* DPRINTF_OSALHEAPTRACE */
{
osalMemHdr_t *hdr = (osalMemHdr_t *)ptr - 1;
halIntState_t intState;
#ifdef DPRINTF_OSALHEAPTRACE
dprintf("osal_mem_free(%lx):%s:%u\n", (unsigned) ptr, fname, lnum);
#endif /* DPRINTF_OSALHEAPTRACE */
HAL_ASSERT(((uint8 *)ptr >= (uint8 *)theHeap) && ((uint8 *)ptr < (uint8 *)theHeap+MAXMEMHEAP));
HAL_ASSERT(hdr->hdr.inUse);
HAL_ENTER_CRITICAL_SECTION( intState ); // Hold off interrupts.
hdr->hdr.inUse = FALSE;
if (ff1 > hdr)
{
ff1 = hdr;
}
#if OSALMEM_PROFILER
#if !OSALMEM_PROFILER_LL
if (osalMemStat != 0) // Don't profile until after the LL block is filled.
#endif
{
uint8 idx;
for (idx = 0; idx < OSALMEM_PROMAX; idx++)
{
if (hdr->hdr.len <= proCnt[idx])
{
break;
}
}
proCur[idx]--;
}
(void)osal_memset((uint8 *)(hdr+1), OSALMEM_REIN, (hdr->hdr.len - OSALMEM_HDRSZ) );
#endif
#if OSALMEM_METRICS
memAlo -= hdr->hdr.len;
blkFree++;
#endif
HAL_EXIT_CRITICAL_SECTION( intState ); // Re-enable interrupts.
}
/*********************************************************************
* @fn ChkReset()
* @brief Check reset bits - if reset cause is unknown, assume a
* brown-out (low power), assume batteries are not reliable,
* hang in a loop and sequence through the LEDs.
* @param None
* @return None
*********************************************************************/
void ChkReset( void )
{
uint8 rib;
// Isolate reset indicator bits
rib = SLEEPSTA & LRESET;
if ( rib == RESETPO )
{
// Put code here to handle Power-On reset
}
else if ( rib == RESETEX )
{
// Put code here to handle External reset
}
else if ( rib == RESETWD )
{
// Put code here to handle WatchDog reset
}
else // Unknown reason - not expected.
{
HAL_ASSERT(0);
}
#if defined HAL_BOARD_CC2530USB || defined HAL_DONGLE_NANO
if (rib != RESETWD) // Embedded boot loaders use RESETWD reason to not touch D+ pullup.
{
HAL_SYSTEM_RESET(); // Trigger a watchdog reset now so any future soft reset works.
}
#endif
}
// =============================================================================
// hal_IfcGetChannel
// -----------------------------------------------------------------------------
/// Get an IFC channel opend in NO auto-disable mode
///
/// @param requestId Describe the direction of the tranfer (rx or
/// tx) and the module to or from which data are to be moved.
/// @param ifcMode Mode of the transfer (Autodisable or not, 8 or 32 bits)
/// @return The channel number got or HAL_UNKNOWN_CHANNEL
// =============================================================================
PROTECTED UINT8 hal_IfcGetChannel(HAL_IFC_REQUEST_ID_T requestId, HAL_IFC_MODE_T ifcMode)
{
UINT8 channel;
// This function is only relevant/available for manual transferts.
HAL_ASSERT(ifcMode == HAL_IFC_SIZE_8_MODE_MANUAL || ifcMode == HAL_IFC_SIZE_32_MODE_MANUAL,
"hal_IfcGetChannel called with an autodisable %d mode", ifcMode);
UINT32 status = hal_SysEnterCriticalSection();
channel = SYS_IFC_CH_TO_USE(hwp_sysIfc->get_ch) ;
if (channel >= SYS_IFC_STD_CHAN_NB)
{
hal_SysExitCriticalSection(status);
return HAL_UNKNOWN_CHANNEL;
}
hwp_sysIfc->std_ch[channel].tc = 0;
hwp_sysIfc->std_ch[channel].start_addr = 0;
g_halModuleIfcChannelOwner[channel] = requestId;
hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId)
| ifcMode
#if (CHIP_HAS_ASYNC_TCU)
| SYS_IFC_CH_RD_HW_EXCH
#endif
| SYS_IFC_ENABLE);
hal_SysExitCriticalSection(status);
return channel;
}
PUBLIC HAL_ERR_T hal_SdioTransferinit(HAL_SDIO_TRANSFER_T* transfer)
{
// UINT8 channel = 0;
// HAL_IFC_REQUEST_ID_T ifcReq = HAL_IFC_NO_REQWEST;
UINT32 length = 0;
UINT32 lengthExp = 0;
HAL_ASSERT((transfer->blockSize>=4) && (transfer->blockSize<=2048),
"Block Length(%d) is invalid!\n", transfer->blockSize);
length = transfer->blockSize;
// The block size register
while (length != 1)
{
length >>= 1;
lengthExp++;
}
// Configure amount of data
hwp_sdmmc2->SDMMC2_BLOCK_CNT = SDMMC2_SDMMC2_BLOCK_CNT(transfer->blockNum);
hwp_sdmmc2->SDMMC2_BLOCK_SIZE = SDMMC2_SDMMC2_BLOCK_SIZE(lengthExp);
hwp_sdmmc2->apbi_ctrl_sdmmc2 = SDMMC2_SOFT_RST_L | SDMMC2_L_ENDIAN(1);
// hwp_sdmmc2->apbi_ctrl_sdmmc = SDMMC2_L_ENDIAN(1);
return HAL_ERR_NO;
// Configure Bytes reordering
//hwp_sdmmc2->apbi_ctrl_sdmmc = SDMMC2_SOFT_RST_L | SDMMC2_L_ENDIAN(1);
}
// =============================================================================
// hal_AifPlayStream
// -----------------------------------------------------------------------------
/// Play a stream, copied from a buffer in memory to the AIF fifos, in infinite
/// mode: when the end of the buffer is reached, playing continues from the
/// beginning.
/// The buffer start address must be aligned on a 32-bit address, and the size
/// must be a multiple of 32 bytes.
///
/// @param playedStream Pointer to the played stream. A stream pointing to
/// a NULL buffer (startAddress field) only enable the audio, without
/// playing data from anywhere.
/// @return HAL_ERR_NO if everything is alright or HAL_ERR_RESOURCE_BUSY if
/// a play is already in process.
// =============================================================================
PUBLIC HAL_ERR_T hal_AifPlayStream(CONST HAL_AIF_STREAM_T* playedStream)
{
UINT32 status;
HAL_ERR_T errStatus = HAL_ERR_NO;
if (hal_SysGetRequestFreq(HAL_SYS_FREQ_AIF) == HAL_SYS_FREQ_32K)
{
HAL_ASSERT(FALSE, "AIF Play Stream when resource not active");
}
status = hal_SysEnterCriticalSection();
if (playedStream->startAddress != NULL)
{
errStatus = hal_AifStream((HAL_AIF_STREAM_T*) playedStream, PLAY);
}
if (errStatus == HAL_ERR_NO)
{
g_halAifPlaying = TRUE;
// Allow symbols to be sent
hwp_aif->ctrl = (g_halAifControlReg | AIF_ENABLE_H_ENABLE) & ~AIF_TX_OFF;
}
hal_SysExitCriticalSection(status);
return errStatus;
}
// =============================================================================
// hal_MapEngineGetVersion
// -----------------------------------------------------------------------------
/// Get the pointer to the version structure of a given module.
///
/// @param id Number of the Module whose version is to be got.
/// @return Pointer to the version structure of said module.
// =============================================================================
PUBLIC HAL_MAP_VERSION_T* hal_MapEngineGetVersion(HAL_MAP_ID_T id)
{
HAL_ASSERT((id >= 0 && id < HAL_MAP_ID_COUNT),
"Bad Hal Engine Module Number");
return g_halMapTable.modules[id].version;
}
/***********************************************************************************
* @fn halRfWriteTxBufSecure
*
* @brief Encrypt and authenticate plaintext then fill TX buffer
*
* @param uint8* data - data buffer. This must be allocated by caller.
* uint8 length - number of bytes
* uint8 encrLength - number of bytes to decrypt
* uint8 authLength - number of bytes to reverse authenticate
* uint8 m - integrity code (m=1,2,3 gives lenght of integrity
* field 4,8,16)
*
* @return none
*/
void halRfWriteTxBufSecure(uint8* data, uint8 length, uint8 encrLength, uint8 authLength, uint8 m)
{
uint8 micLength;
// Check range of m
#if 0 // POOH
HAL_ASSERT(m<=4);
#else
if( m > 4 )
{
DEBUG_MSG_ASSERT;
}
#endif
if(m>0) {
micLength = 0x2<<m;
}
else if(m==0) {
micLength=0;
}
// Write packet to work buffer
CC2520_MEMWR(ADDR_TX, length, data);
// skip the length byte and start from the next byte in TXBUF
// Outgoing frame uses nonce_tx
CC2520_CCM(HIGH_PRIORITY,ADDR_KEY/16, encrLength, ADDR_NONCE_TX/16, ADDR_TX+1, 0, authLength, m);
WAIT_DPU_DONE_H();
// copy from work buffer to TX FIFO
CC2520_TXBUFCP(HIGH_PRIORITY, ADDR_TX, length+micLength, NULL);
WAIT_DPU_DONE_H();
}
// ============================================================================
// hal_I2cReadRawByte
// ----------------------------------------------------------------------------
/// This function completes the 2 phase read cycle which was previously
/// initiated by the hal_I2cSendRawByte() function with 2PHASE_RD_PH1 as the
/// command. This function requires the command mask to be passed as a
/// parameter, but for the SCCB, it should be (Stop | Read | NACK)
///
/// @param id ID of the I2C bus
/// @param CmdMask this is the command mask required for the final phase of the
/// SCCB read cycle.
/// @return Data byte read by the I2C interface
/// FIXME Shouldn't we lock the bus since the beginning of hal_I2cSendRawByte
/// and only release it here ?
// ============================================================================
PUBLIC UINT8 hal_I2cReadRawByte(HAL_I2C_BUS_ID_T id, UINT32 CmdMask)
{
HAL_ASSERT(id<HAL_I2C_BUS_ID_QTY && g_halI2cOpened[id],
g_halI2cErrStrIdNotActive, id);
HWP_I2C_MASTER_T* CONST i2cMaster = g_halI2cMasterAddr[id];
// FIXME How do we know that what is returned there is an error ?
// and not the received byte ?
HAL_I2C_TAKE_BUS(id);
while(i2cMaster -> STATUS & I2C_MASTER_TIP);
i2cMaster->IRQ_CLR = I2C_MASTER_IRQ_CLR;
// Read value - send no acknowledge - send stop condition/bit
i2cMaster->CMD = CmdMask;
// Polling on the TIP flag
/* while(i2cMaster -> STATUS & I2C_MASTER_TIP); */
while(!(i2cMaster -> STATUS & I2C_MASTER_IRQ_STATUS));
i2cMaster->IRQ_CLR = I2C_MASTER_IRQ_CLR;
HAL_I2C_RELEASE_BUS(id);
return((UINT8)i2cMaster->TXRX_BUFFER);
}
// ============================================================================
// hal_I2cSendRawByte
// ----------------------------------------------------------------------------
/// This function sends a single byte on the I2C interface
/// It is not designed for use in the real I2C protocol, but allows access
/// for non-standard usages such as SCCB for the Omnivision Camera control
///
/// @param id ID of the I2C bus
/// @param SendByte raw data byte to be sent.
/// @param CmdMask this is the command associated with this byte. It must
/// be sent at the same time so the two actions (write to the data fifo and
/// issue the command) are done together.
/// @return HAL_ERR_NO if everything was OK, otherwise Resource Busy if the
/// bus is in use
// ============================================================================
PUBLIC HAL_ERR_T hal_I2cSendRawByte(HAL_I2C_BUS_ID_T id, UINT8 SendByte, UINT32 CmdMask)
{
HAL_ASSERT(id<HAL_I2C_BUS_ID_QTY && g_halI2cOpened[id],
g_halI2cErrStrIdNotActive, id);
HWP_I2C_MASTER_T* CONST i2cMaster = g_halI2cMasterAddr[id];
HAL_I2C_TAKE_BUS(id);
// TODO: Don't check bus right now, but need to do some check later
// test bus availability
// if (i2cMaster->STATUS & (I2C_MASTER_TIP|I2C_MASTER_BUSY))
// {
// HAL_I2C_RELEASE_BUS(id);
// return HAL_ERR_RESOURCE_BUSY;
// }
while(i2cMaster -> STATUS & I2C_MASTER_TIP);
// Write slave address
i2cMaster->TXRX_BUFFER = (REG32)SendByte;
i2cMaster->CMD = (REG32)CmdMask;
HAL_I2C_RELEASE_BUS(id);
return HAL_ERR_NO;
}
// ============================================================================
// hal_I2cWakeup
// ----------------------------------------------------------------------------
/// Wake-Up I2C driver.
///
/// @param id ID of the I2C bus
// ============================================================================
PROTECTED VOID hal_I2cWakeup(HAL_I2C_BUS_ID_T id)
{
HAL_ASSERT(id<HAL_I2C_BUS_ID_QTY && g_halI2cOpened[id],
g_halI2cErrStrIdNotActive, id);
// Allow usage.
//g_halI2cInUse[id] = FALSE;
}
void main(void)
{
halMcuInit();
hal_led_init();
hal_uart_init();
//Uart0Init(0, 0);
printf("s rssi: d\r\n");
//Uart0Init(unsigned char StopBits,unsigned char Parity)
if (FAILED == halRfInit()) {
HAL_ASSERT(FALSE);
}
// Config basicRF
basicRfConfig.panId = PAN_ID;
basicRfConfig.channel = RF_CHANNEL;
basicRfConfig.ackRequest = TRUE;
#ifdef SECURITY_CCM
basicRfConfig.securityKey = key;
#endif
// Initialize BasicRF
#if NODE_TYPE
basicRfConfig.myAddr = SEND_ADDR;
#else
basicRfConfig.myAddr = RECV_ADDR;
#endif
if(basicRfInit(&basicRfConfig)==FAILED) {
HAL_ASSERT(FALSE);
}
#if NODE_TYPE
//uWaveInit();
dht11_io_init();
rfSendData();
#else
rfRecvData();
#endif
}
/***************************************************************************//**
* WD_reload()
* See "core_watchdog.h" for details of how to use this function.
*/
void
WD_reload
(
wd_instance_t *instance
)
{
HAL_ASSERT( instance != NULL_instance )
HAL_set_32bit_reg( instance->base_address, WDOGREFRESH, 1 );
}
/***************************************************************************//**
* TMR_clear_int()
* See "core_timer.h" for details of how to use this function.
*/
void
TMR_clear_int
(
timer_instance_t * this_timer
)
{
HAL_ASSERT( this_timer != NULL_timer_instance )
HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 );
}
/***************************************************************************//**
* WD_disable()
* See "core_watchdog.h" for details of how to use this function.
*/
void
WD_disable
(
wd_instance_t *instance
)
{
HAL_ASSERT( instance != NULL_instance )
HAL_set_32bit_reg_field( instance->base_address, WDOGCONTROL_WATCHDOG_ENABLE, 0 );
}
/***************************************************************************//**
* TMR_enable_int()
* See "core_timer.h" for details of how to use this function.
*/
void
TMR_enable_int
(
timer_instance_t * this_timer
)
{
HAL_ASSERT( this_timer != NULL_timer_instance )
HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 );
}
/***************************************************************************//**
* TMR_stop()
* See "core_timer.h" for details of how to use this function.
*/
void
TMR_stop
(
timer_instance_t * this_timer
)
{
HAL_ASSERT( this_timer != NULL_timer_instance )
HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 0 );
}
PROTECTED VOID hal_AifSleep(VOID)
{
if (hal_AifResourceMgmt() == TRUE)
{
HAL_ASSERT(FALSE, "AIF Sleep called when AIF still in use!");
}
// release the resource
hal_SysRequestFreq(HAL_SYS_FREQ_AIF, HAL_SYS_FREQ_32K, NULL);
}
// =============================================================================
// hal_PwmUpdateDivider
// -----------------------------------------------------------------------------
/// Update the PWM divider to cope with the new system clock.
// =============================================================================
PRIVATE VOID hal_PwmUpdateDivider(HAL_SYS_FREQ_T freq)
{
UINT32 divider;
switch (freq)
{
case HAL_SYS_FREQ_13M:
divider = HAL_PWM_BASE_DIVIDER*1;
break;
case HAL_SYS_FREQ_26M:
divider = HAL_PWM_BASE_DIVIDER*2;
break;
case HAL_SYS_FREQ_39M:
divider = HAL_PWM_BASE_DIVIDER*3;
break;
case HAL_SYS_FREQ_52M:
divider = HAL_PWM_BASE_DIVIDER*4;
break;
case HAL_SYS_FREQ_78M:
divider = HAL_PWM_BASE_DIVIDER*6;
break;
case HAL_SYS_FREQ_104M:
divider = HAL_PWM_BASE_DIVIDER*8;
break;
case HAL_SYS_FREQ_156M:
divider = HAL_PWM_BASE_DIVIDER*12;
break;
//
// FIXME
case HAL_SYS_FREQ_32K:
divider = 1;
break;
default:
// Checks if some PWM is enabled. We cannot switch
// to 32k if a PWM is enabled.
if (((hwp_pwm->PWL0_Config & PWM_PWL0_EN_H) != 0) ||
((hwp_pwm->PWL1_Config & PWM_PWL1_EN_H) != 0) ||
((hwp_pwm->PWT_Config & PWM_PWT_ENABLE) != 0))
{
HAL_ASSERT(FALSE, "Bad system frequency: %d", freq);
}
// This will change the divider, but nothing is enabled.
divider = 0;
}
hal_SysSetupClkPwm(divider);
}
// =============================================================================
// hal_IfcSetStartAddress
// -----------------------------------------------------------------------------
/// Set the start address of a previously opened (with hal_IfcGetChannel)
/// IFC channel.
///
/// Should be used only when a channel has been locked.
///
/// @param channel Opened channel whose start address will be set.
/// @param startAddress Set start address of the channel.
// =============================================================================
PROTECTED VOID hal_IfcSetStartAddress(UINT8 channel, CONST UINT8* startAddress)
{
// channel number too big
IFC_ASSERT(channel < SYS_IFC_STD_CHAN_NB, channel);
HAL_ASSERT(hwp_sysIfc->std_ch[channel].tc == 0, "Attempt to change an IFC start_address "
"while tc != 0 (==%d), channel=%d", hwp_sysIfc->std_ch[channel].tc, channel);
// Writing in the Tc register adds the number written
// to the counter of bytes yet to transfer
hwp_sysIfc->std_ch[channel].start_addr = (UINT32) startAddress;
}
/*-------------------------------------------------------------------------*//**
* PWM_disable()
* See "core_pwm.h" for details of how to use this function.
*/
void PWM_disable
(
pwm_instance_t * pwm_inst,
pwm_id_t pwm_id
)
{
uint8_t pwm_enables;
uint8_t pwm_id_mask;
/* Assertion will ensure correct PWM output has been selected. */
HAL_ASSERT( pwm_id >= PWM_1 )
HAL_ASSERT( pwm_id <= PWM_16 )
if ( (pwm_id >= PWM_1) && (pwm_id <= PWM_16 ))
{
pwm_id_mask = g_pwm_id_mask_lut[pwm_id];
if ( pwm_id < PWM_9 )
{
pwm_enables = HAL_get_8bit_reg( pwm_inst->address, PWM_ENABLE_1 );
pwm_enables &= (uint8_t)~pwm_id_mask;
HAL_set_8bit_reg
(
pwm_inst->address,
PWM_ENABLE_1,
(uint_fast8_t)pwm_enables
);
}
else
{
pwm_enables = HAL_get_8bit_reg( pwm_inst->address, PWM_ENABLE_2 );
pwm_enables &= (uint8_t)~pwm_id_mask;
HAL_set_8bit_reg
(
pwm_inst->address,
PWM_ENABLE_2,
(uint_fast8_t)pwm_enables
);
}
}
}
/***************************************************************************//**
* WD_init()
* See "core_watchdog.h" for details of how to use this function.
*/
void
WD_init
(
wd_instance_t *instance,
addr_t base,
uint32_t value,
uint32_t scale
)
{
HAL_ASSERT( instance != NULL_instance )
HAL_ASSERT( scale <= WD_PRESCALER_DIV_1024 )
instance->base_address = base;
/* Make sure the watchdog timer is disabled. */
HAL_set_32bit_reg_field( instance->base_address, WDOGCONTROL_WATCHDOG_ENABLE, 0 );
/* Configure prescaler and load value. */
HAL_set_32bit_reg_field( instance->base_address, WDOGCONTROL_PRESCALE, scale );
HAL_set_32bit_reg( instance->base_address, WDOGLOAD, value );
}
// ============================================================================
// hal_I2cClose
// ----------------------------------------------------------------------------
/// This function closes the I2C module.
///
/// @param id ID of the I2C bus
// ============================================================================
PUBLIC VOID hal_I2cClose(HAL_I2C_BUS_ID_T id)
{
HAL_ASSERT(id<HAL_I2C_BUS_ID_QTY && g_halI2cOpened[id],
g_halI2cErrStrIdNotActive, id);
#if (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
// I2C needs 2 sets of power supply, one for I/O, and the other for pull-up resistor
pmd_EnablePower(PMD_POWER_I2C, FALSE);
#endif // (CHIP_ASIC_ID == CHIP_ASIC_ID_GALLITE)
// I2C is never really closed once initialized
}
