Ejemplo n.º 1
0
/*************************************************************************//**
*****************************************************************************/
void halPhyInit(void)
{
  HAL_GPIO_PHY_SLP_TR_out();
  HAL_GPIO_PHY_SLP_TR_clr();
  HAL_GPIO_PHY_RST_out();
  HAL_GPIO_PHY_IRQ_in();
  HAL_GPIO_PHY_CS_out();
  HAL_GPIO_PHY_MISO_in();
  HAL_GPIO_PHY_MOSI_out();
  HAL_GPIO_PHY_SCK_out();

  SPCR = ((1 << SPE) | (1 << MSTR));
  SPSR = (1 << SPI2X);
}
Ejemplo n.º 2
0
/*************************************************************************//**
*****************************************************************************/
void halPhyInit(void)
{
  // Configure IO pins
  HAL_GPIO_PHY_SLP_TR_out();
  HAL_GPIO_PHY_SLP_TR_clr();
  HAL_GPIO_PHY_RST_out();
  HAL_GPIO_PHY_IRQ_in();
  HAL_GPIO_PHY_IRQ_pmuxen();
  HAL_GPIO_PHY_CS_out();
  HAL_GPIO_PHY_MISO_in();
  HAL_GPIO_PHY_MISO_pmuxen();
  HAL_GPIO_PHY_MOSI_out();
  HAL_GPIO_PHY_MOSI_pmuxen();
  HAL_GPIO_PHY_SCK_out();
  HAL_GPIO_PHY_SCK_pmuxen();

  // Configure SPI
  PORT->Group[HAL_GPIO_PORTA].PMUX[9].bit.PMUXE = 2/*C*/; // MOSI
  PORT->Group[HAL_GPIO_PORTA].PMUX[9].bit.PMUXO = 2/*C*/; // SCK
  PORT->Group[HAL_GPIO_PORTA].PMUX[8].bit.PMUXE = 2/*C*/; // MISO

  PM->APBCMASK.reg |= PM_APBCMASK_SERCOM1;

  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(SERCOM1_GCLK_ID_CORE) |
      GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);

  SERCOM1->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_RXEN;
  halPhySpiSync();

#if F_CPU <= 16000000
  SERCOM1->SPI.BAUD.reg = 0;
#elif F_CPU <= 32000000
  SERCOM1->SPI.BAUD.reg = 1;
#elif F_CPU <= 48000000
  SERCOM1->SPI.BAUD.reg = 2;
#else
  #error Unsupported frequency
#endif

  SERCOM1->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_MODE_SPI_MASTER |
      SERCOM_SPI_CTRLA_DIPO(0) | SERCOM_SPI_CTRLA_DOPO;
  halPhySpiSync();
}
Ejemplo n.º 3
0
/*************************************************************************//**
*****************************************************************************/
void halPhyInit(void)
{
  HAL_GPIO_PHY_SLP_TR_out();
  HAL_GPIO_PHY_RST_out();
  HAL_GPIO_PHY_IRQ_in();
  HAL_GPIO_PHY_CS_out();
  HAL_GPIO_PHY_MISO_in();
  HAL_GPIO_PHY_MOSI_out();
  HAL_GPIO_PHY_SCK_out();

#if F_CPU == 4000000 || F_CPU == 8000000 || F_CPU == 12000000
  SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_CLK2X_bm;
#elif F_CPU == 16000000
  SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm;
#elif F_CPU == 32000000
  SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_CLK2X_bm | SPI_PRESCALER0_bm;
#else
  #error Unsupported F_CPU
#endif
}
Ejemplo n.º 4
0
/*************************************************************************//**
*****************************************************************************/
void halPhyInit(void)
{
  HAL_GPIO_PHY_SLP_TR_out();
  HAL_GPIO_PHY_SLP_TR_clr();
  HAL_GPIO_PHY_RST_out();
  HAL_GPIO_PHY_IRQ_in();
  HAL_GPIO_PHY_CS_out();
  HAL_GPIO_PHY_MISO_in();
  HAL_GPIO_PHY_MOSI_out();
  HAL_GPIO_PHY_SCK_out();

  SPCR = ((1 << SPE) | (1 << MSTR));
  SPSR = (1 << SPI2X);

#if defined(PLATFORM_ZIGBIT)
  EICRB |= (1 << ISC51) | (1 << ISC50);
  EIMSK |= (1 << INT5);
#elif defined(PLATFORM_RCB231)
  EICRA |= (1 << ISC01) | (1 << ISC00);
  EIMSK |= (1 << INT0);
#endif
}