int
hal_enable_profile_timer(int resolution)
{
// Run periodic timer interrupt for profile
cyg_uint16 piscr;
int period = resolution / 100;
// Attach pit arbiter.
HAL_INTERRUPT_ATTACH (PIT_IRQ,
&hal_arbitration_isr_pit, ID_PIT, 0);
HAL_INTERRUPT_UNMASK (PIT_IRQ);
// Attach pit isr.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
ID_PIT, 0);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, PIT_IRQ_LEVEL);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
// Set period.
HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC,
(2*period) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
// Enable.
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr |= CYGARC_REG_IMM_PISCR_PTE;
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
return resolution;
}
void sparc_ex_main( void )
{
int i;
CYG_TEST_INIT();
for ( i = CYGNUM_HAL_EXCEPTION_MIN; i <= CYGNUM_HAL_EXCEPTION_MAX; i++ ){
int j;
HAL_TRANSLATE_VECTOR( i, j );
HAL_INTERRUPT_ATTACH( j, &fail_exception_handler, j, 0 );
// we must also ensure that eCos handles the exception;
// do not drop into CygMon or equivalent.
// Leave USER_TRAP undisturbed so that breakpoints work.
if ( CYGNUM_HAL_VECTOR_USER_TRAP != i ) {
extern void hal_default_exception_vsr( void );
HAL_VSR_SET( i, (CYG_ADDRESS)hal_default_exception_vsr, NULL );
}
}
HAL_TRANSLATE_VECTOR( CYGNUM_HAL_VECTOR_UNALIGNED, i );
HAL_INTERRUPT_DETACH( i, &fail_exception_handler );
HAL_INTERRUPT_ATTACH( i, &skip_exception_handler, i, 0 );
CYG_TEST_INFO( "Vectors attached OK; calling do_test" );
do_test();
CYG_TEST_EXIT( "Done" );
}
externC void cyg_drv_interrupt_attach( cyg_handle_t interrupt )
{
cyg_interrupt *intr = (cyg_interrupt *)interrupt;
CYG_REPORT_FUNCTION();
CYG_ASSERT( intr->vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( intr->vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_INTERRUPT_SET_LEVEL( intr->vector, intr->priority );
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
CYG_ASSERT( intr->next == NULL , "cyg_interrupt already on a list");
{
cyg_uint32 index;
HAL_TRANSLATE_VECTOR( intr->vector, index );
if( chain_list[index] == NULL )
{
// First Interrupt on this chain, just assign it and
// register the chain_isr with the HAL.
chain_list[index] = intr;
HAL_INTERRUPT_ATTACH( intr->vector, chain_isr,
&chain_list[index], NULL );
}
else
{
// There are already interrupts chained, add this one into
// the chain in priority order.
cyg_interrupt **p = &chain_list[index];
while( *p != NULL )
{
cyg_interrupt *n = *p;
if( n->priority < intr->priority ) break;
p = &n->next;
}
intr->next = *p;
*p = intr;
}
}
#else
HAL_INTERRUPT_ATTACH( intr->vector, intr->isr, intr->data, intr );
#endif
CYG_REPORT_RETURN();
}
// Profiling timer setup
int hal_enable_profile_timer(int resolution)
{
cyg_uint32 period;
// Calculate how many timer ticks the requested resolution in
// microseconds equates to. We do this calculation in 64 bit
// arithmetic to avoid overflow.
period = (cyg_uint32)((((cyg_uint64)resolution) *
((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL);
CYG_ASSERT(period < 0x10000, "Invalid profile timer resolution"); // 16 bits only
// Attach ISR
HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0);
HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE);
// Disable counter
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
// Set registers
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
AT91_TC_CMR_CLKS_MCK32); // Use MCLK/32
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_RC, period);
// Start timer
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Enable timer interrupt
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_IER, AT91_TC_IER_CPC);
return resolution;
}
void
watchdogInt(void) {
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_WATCHDOG,
wd_ISR,
NULL, NULL);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_WATCHDOG);
diag_printf("Watchdog Int installed!!!\n");
}
// -------------------------------------------------------------------------
// Variant specific interrupt setup
externC void
hal_variant_IRQ_init(void)
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
externC void
hal_variant_IRQ_init(void)
{
HAL_INTERRUPT_MASK (CYGNUM_EXPANSION);
/* clear the mask register */
HAL_WRITE_UINT32(INTR_MASK_REG, 0); /* all expansion interrupts are masked */
HAL_INTERRUPT_ATTACH (CYGNUM_EXPANSION, &hal_extended_isr, 0, 0);
HAL_INTERRUPT_UNMASK (CYGNUM_EXPANSION);
}
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
{
CYG_ADDRWORD vector = 2*(1 + adata->priority);
if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
{
HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, 0);
HAL_INTERRUPT_UNMASK(vector);
}
else
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating
// the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_insert(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#else
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
}
externC void
hal_variant_IRQ_init(void)
{
#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
// Attach first-level CPM arbiter to the configured SIU level and
// enable CPM interrupts.
#define ID_CPM 0xDEAD
#define CYGPRI_SIU_LVL (CYGNUM_HAL_INTERRUPT_SIU_LVL0 \
+CYGHWR_HAL_POWERPC_MPC860_CPM_LVL*2)
HAL_INTERRUPT_ATTACH (CYGPRI_SIU_LVL, &hal_arbitration_isr_cpm, ID_CPM, 0);
HAL_INTERRUPT_UNMASK (CYGPRI_SIU_LVL);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_CPM,
CYGHWR_HAL_POWERPC_MPC860_CPM_LVL);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_CPM);
#endif
}
externC void
hal_variant_IRQ_init(void)
{
// Mask off everything. This guarantees that we can safely install a handler on the decrementer
// later on
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ0);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ1);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ2);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ3);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ4);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ5);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ6);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ7);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL0);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL1);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL2);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL3);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL4);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL5);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL6);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
// GDB-CTRLC
// Install a default arbiter for serial interrupts. This allows
// to make a boot monitor simply turn on the required Rx interrupt
// and still be delivered the necessary default isr. Without this,
// redboot would be informed of a level interrupt on the SIU instead
// of the Rx interrupt that really happened.
// Make sure the interrupts are set up on the correct level
sci_arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI;
sci_arbiter.data = 0;
sci_arbiter.arbiter = hal_arbitration_isr_sci;
hal_mpc5xx_install_arbitration_isr(&sci_arbiter);
HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
#endif
}
