Ejemplo n.º 1
0
int xhci_hub_setup_ports(struct xhci_hcd *xhci)
{
	u32 offset, tmp_offset;
	__le32 __iomem *addr, *tmp_addr;
	unsigned int num_ports;
	int i, cap_count = 0;

	offset = HCC_EXT_CAPS(xhci->hcc_params);
	if (offset == 0) {
		dev_err(xhci->dev, "No Extended Capability Registers\n");
		return -ENODEV;
	}

	addr = &xhci->cap_regs->hc_capbase + offset;

	/* count extended protocol capability entries for later caching */
	tmp_addr = addr;
	tmp_offset = offset;
	do {
		u32 cap_id = readl(tmp_addr);

		if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
			cap_count++;

		tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id);
		tmp_addr += tmp_offset;
	} while (tmp_offset);

	num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
	xhci->port_array = xzalloc(num_ports * sizeof(*xhci->port_array));
	xhci->ext_caps = xzalloc(cap_count * sizeof(*xhci->ext_caps));

	while (1) {
		u32 cap_id = readl(addr);

		if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
			xhci_add_in_port(xhci, num_ports, addr,
					 (u8)XHCI_EXT_PORT_MAJOR(cap_id),
					 cap_count);
		offset = XHCI_EXT_CAPS_NEXT(cap_id);
		if (!offset || xhci->num_usb_ports == num_ports)
                        break;
		addr += offset;
	}

	if (xhci->num_usb_ports == 0) {
		dev_err(xhci->dev, "No ports on the roothubs?\n");
		return -ENODEV;
	}

	xhci->usb_ports = xzalloc(num_ports * sizeof(*xhci->usb_ports));
	for (i = 0; i < num_ports; i++)
		xhci->usb_ports[i] = &xhci->op_regs->port_status_base +
			NUM_PORT_REGS * i;
	memcpy(&xhci->usb_info, &usb_rh_info, sizeof(usb_rh_info));
	xhci_setup_usb2_hub_descriptor(xhci);

	return 0;
}
Ejemplo n.º 2
0
static int ehci_hc_reset (struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
	u32			temp;
	unsigned		count = 256/4;

	spin_lock_init (&ehci->lock);

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
	dbg_hcs_params (ehci, "reset");
	dbg_hcc_params (ehci, "reset");

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = readl (&ehci->caps->hcs_params);

#ifdef	CONFIG_PCI
	if (hcd->self.controller->bus == &pci_bus_type) {
		struct pci_dev	*pdev = to_pci_dev(hcd->self.controller);

		switch (pdev->vendor) {
		case PCI_VENDOR_ID_TDI:
			if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
				ehci->is_tdi_rh_tt = 1;
				tdi_reset (ehci);
			}
			break;
		case PCI_VENDOR_ID_AMD:
			/* AMD8111 EHCI doesn't work, according to AMD errata */
			if (pdev->device == 0x7463) {
				ehci_info (ehci, "ignoring AMD8111 (errata)\n");
				return -EIO;
			}
			break;
		}

		/* optional debug port, normally in the first BAR */
		temp = pci_find_capability (pdev, 0x0a);
		if (temp) {
			pci_read_config_dword(pdev, temp, &temp);
			temp >>= 16;
			if ((temp & (3 << 13)) == (1 << 13)) {
				temp &= 0x1fff;
				ehci->debug = hcd->regs + temp;
				temp = readl (&ehci->debug->control);
				ehci_info (ehci, "debug port %d%s\n",
					HCS_DEBUG_PORT(ehci->hcs_params),
					(temp & DBGP_ENABLED)
						? " IN USE"
						: "");
				if (!(temp & DBGP_ENABLED))
					ehci->debug = NULL;
			}
		}

		temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
	} else
Ejemplo n.º 3
0
static int ehci_hc_reset (struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
	u32			temp;
#ifndef CONFIG_FSL_USB20
	unsigned		count = 256/4;
#endif

	spin_lock_init (&ehci->lock);

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
	dbg_hcs_params (ehci, "reset");
	dbg_hcc_params (ehci, "reset");

#ifdef CONFIG_FSL_USB20
	mpc8349_usb_reset ();
	ehci->is_tdi_rh_tt = 1;
#endif

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = readl (&ehci->caps->hcs_params);

#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_USB20)
	if (hcd->self.controller->bus == &pci_bus_type) {
		struct pci_dev	*pdev = to_pci_dev(hcd->self.controller);

		switch (pdev->vendor) {
		case PCI_VENDOR_ID_TDI:
			if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
				ehci->is_tdi_rh_tt = 1;
				tdi_reset (ehci);
			}
			break;
		case PCI_VENDOR_ID_AMD:
			/* AMD8111 EHCI doesn't work, according to AMD errata */
			if (pdev->device == 0x7463) {
				ehci_info (ehci, "ignoring AMD8111 (errata)\n");
				return -EIO;
			}
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NVidia reports that certain chips don't handle
			 * QH, ITD, or SITD addresses above 2GB.  (But TD,
			 * data buffer, and periodic schedule are normal.)
			 */
			switch (pdev->device) {
			case 0x003c:	/* MCP04 */
			case 0x005b:	/* CK804 */
			case 0x00d8:	/* CK8 */
			case 0x00e8:	/* CK8S */
				if (pci_set_consistent_dma_mask(pdev,
							DMA_31BIT_MASK) < 0)
					ehci_warn (ehci, "can't enable NVidia "
						"workaround for >2GB RAM\n");
				break;
			}
			break;
		}

		/* optional debug port, normally in the first BAR */
		temp = pci_find_capability (pdev, 0x0a);
		if (temp) {
			pci_read_config_dword(pdev, temp, &temp);
			temp >>= 16;
			if ((temp & (3 << 13)) == (1 << 13)) {
				temp &= 0x1fff;
				ehci->debug = hcd->regs + temp;
				temp = readl (&ehci->debug->control);
				ehci_info (ehci, "debug port %d%s\n",
					HCS_DEBUG_PORT(ehci->hcs_params),
					(temp & DBGP_ENABLED)
						? " IN USE"
						: "");
				if (!(temp & DBGP_ENABLED))
					ehci->debug = NULL;
			}
		}

		temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
	} else