void DumpAR6KDevState(AR6K_DEVICE *pDev)
{
int status;
AR6K_IRQ_ENABLE_REGISTERS regs;
AR6K_IRQ_PROC_REGISTERS procRegs;
LOCK_AR6K(pDev);
/* copy into our temp area */
A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
UNLOCK_AR6K(pDev);
/* load the register table from the device */
status = HIFReadWrite(pDev->HIFDevice,
HOST_INT_STATUS_ADDRESS,
(u8 *)&procRegs,
AR6K_IRQ_PROC_REGS_SIZE,
HIF_RD_SYNC_BYTE_INC,
NULL);
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DumpAR6KDevState : Failed to read register table (%d) \n",status));
return;
}
DevDumpRegisters(pDev,&procRegs,®s);
if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);
}
/* dump any bus state at the HIF layer */
HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
}
/* set HTC/Mbox operational parameters, this can only be called when the target is in the
* BMI phase */
A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice,
A_UINT32 TargetType,
A_UINT32 MboxIsrYieldValue,
A_UINT8 HtcControlBuffers)
{
A_STATUS status;
A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
do {
/* get the block sizes */
status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
blocksizes, sizeof(blocksizes));
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
break;
}
/* note: we actually get the block size for mailbox 1, for SDIO the block
* size on mailbox 0 is artificially set to 1 */
/* must be a power of 2 */
A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
if (HtcControlBuffers != 0) {
/* set override for number of control buffers to use */
blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16;
}
/* set the host interest area for the block size */
status = BMIWriteMemory(hifDevice,
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
(A_UCHAR *)&blocksizes[1],
4);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
break;
}
AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
if (MboxIsrYieldValue != 0) {
/* set the host interest area for the mbox ISR yield limit */
status = BMIWriteMemory(hifDevice,
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
(A_UCHAR *)&MboxIsrYieldValue,
4);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
break;
}
}
} while (FALSE);
return status;
}
A_STATUS
ar6000_get_hif_dev(HIF_DEVICE *device, void *config)
{
A_STATUS status;
status = HIFConfigureDevice(device,
HIF_DEVICE_GET_OS_DEVICE,
(HIF_DEVICE_OS_DEVICE_INFO *)config,
sizeof(HIF_DEVICE_OS_DEVICE_INFO));
return status;
}
A_STATUS
BMIDone(HIF_DEVICE *device, struct ol_ath_softc_net80211 *scn)
{
A_STATUS status;
A_UINT32 cid;
if (scn->bmiDone) {
AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
return A_OK;
}
AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
#if defined(A_SIMOS_DEVHOST)
/* Let HIF layer know that BMI phase is done.
* Note that this call enqueues a bunch of receive buffers,
* so it is important that this complete before we tell the
* target about BMI_DONE.
*/
(void)HIFConfigureDevice(device, HIF_BMI_DONE, NULL, 0);
#endif
scn->bmiDone = TRUE;
cid = BMI_DONE;
if (!scn->pBMICmdBuf) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("pBMICmdBuf is NULL\n"));
return A_ERROR;
}
A_MEMCPY(scn->pBMICmdBuf,&cid,sizeof(cid));
status = HIFExchangeBMIMsg(device, scn->pBMICmdBuf, sizeof(cid), NULL, NULL, 0);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
return A_ERROR;
}
if (scn->pBMICmdBuf) {
OS_FREE_CONSISTENT(scn->sc_osdev, MAX_BMI_CMDBUF_SZ,
scn->pBMICmdBuf, scn->BMICmd_pa, OS_GET_DMA_MEM_CONTEXT(scn, bmicmd_dmacontext));
scn->pBMICmdBuf = NULL;
scn->BMICmd_pa = 0;
}
if (scn->pBMIRspBuf) {
OS_FREE_CONSISTENT(scn->sc_osdev, MAX_BMI_CMDBUF_SZ,
scn->pBMIRspBuf, scn->BMIRsp_pa, OS_GET_DMA_MEM_CONTEXT(scn, bmirsp_dmacontext));
scn->pBMIRspBuf = NULL;
scn->BMIRsp_pa = 0;
}
AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
return A_OK;
}
int
ar6000_get_hif_dev(struct hif_device *device, void *config)
{
int status;
status = HIFConfigureDevice(device,
HIF_DEVICE_GET_OS_DEVICE,
(struct hif_device_os_device_info *)config,
sizeof(struct hif_device_os_device_info));
return status;
}
/* BMI Access routines */
A_STATUS
bmiBufferSend(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length)
{
A_STATUS status;
A_UINT32 timeout;
A_UINT32 address;
static A_UINT32 cmdCredits;
A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
&mboxAddress[0], sizeof(mboxAddress));
cmdCredits = 0;
timeout = BMI_COMMUNICATION_TIMEOUT;
while(timeout-- && !cmdCredits) {
/* Read the counter register to get the command credits */
address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
/* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
* a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to
* make all HIF accesses 4-byte aligned */
status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4,
HIF_RD_SYNC_BYTE_INC, NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
return A_ERROR;
}
/* the counter is only 8=bits, ignore anything in the upper 3 bytes */
cmdCredits &= 0xFF;
}
if (cmdCredits) {
address = mboxAddress[ENDPOINT1];
status = HIFReadWrite(device, address, buffer, length,
HIF_WR_SYNC_BYTE_INC, NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
return A_ERROR;
}
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n"));
return A_ERROR;
}
return status;
}
A_STATUS
bmiBufferReceive(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length,
A_BOOL want_timeout)
{
A_STATUS status;
A_UINT32 address;
A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
HIF_PENDING_EVENTS_INFO hifPendingEvents;
static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL;
if (!pendingEventsFuncCheck) {
/* see if the HIF layer implements an alternative function to get pending events
* do this only once! */
HIFConfigureDevice(device,
HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
&getPendingEventsFunc,
sizeof(getPendingEventsFunc));
pendingEventsFuncCheck = TRUE;
}
HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
&mboxAddress[0], sizeof(mboxAddress));
/*
* During normal bootup, small reads may be required.
* Rather than issue an HIF Read and then wait as the Target
* adds successive bytes to the FIFO, we wait here until
* we know that response data is available.
*
* This allows us to cleanly timeout on an unexpected
* Target failure rather than risk problems at the HIF level. In
* particular, this avoids SDIO timeouts and possibly garbage
* data on some host controllers. And on an interconnect
* such as Compact Flash (as well as some SDIO masters) which
* does not provide any indication on data timeout, it avoids
* a potential hang or garbage response.
*
* Synchronization is more difficult for reads larger than the
* size of the MBOX FIFO (128B), because the Target is unable
* to push the 129th byte of data until AFTER the Host posts an
* HIF Read and removes some FIFO data. So for large reads the
* Host proceeds to post an HIF Read BEFORE all the data is
* actually available to read. Fortunately, large BMI reads do
* not occur in practice -- they're supported for debug/development.
*
* So Host/Target BMI synchronization is divided into these cases:
* CASE 1: length < 4
* Should not happen
*
* CASE 2: 4 <= length <= 128
* Wait for first 4 bytes to be in FIFO
* If CONSERVATIVE_BMI_READ is enabled, also wait for
* a BMI command credit, which indicates that the ENTIRE
* response is available in the the FIFO
*
* CASE 3: length > 128
* Wait for the first 4 bytes to be in FIFO
*
* For most uses, a small timeout should be sufficient and we will
* usually see a response quickly; but there may be some unusual
* (debug) cases of BMI_EXECUTE where we want an larger timeout.
* For now, we use an unbounded busy loop while waiting for
* BMI_EXECUTE.
*
* If BMI_EXECUTE ever needs to support longer-latency execution,
* especially in production, this code needs to be enhanced to sleep
* and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
* a function of Host processor speed.
*/
if (length >= 4) { /* NB: Currently, always true */
/*
* NB: word_available is declared static for esoteric reasons
* having to do with protection on some OSes.
*/
static A_UINT32 word_available;
A_UINT32 timeout;
word_available = 0;
timeout = BMI_COMMUNICATION_TIMEOUT;
while((!want_timeout || timeout--) && !word_available) {
if (getPendingEventsFunc != NULL) {
status = getPendingEventsFunc(device,
&hifPendingEvents,
NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n"));
break;
}
if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) {
word_available = 1;
}
continue;
}
status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available,
sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n"));
return A_ERROR;
}
/* We did a 4-byte read to the same register; all we really want is one bit */
word_available &= (1 << ENDPOINT1);
}
if (!word_available) {
AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n"));
return A_ERROR;
}
}
#define CONSERVATIVE_BMI_READ 0
#if CONSERVATIVE_BMI_READ
/*
* This is an extra-conservative CREDIT check. It guarantees
* that ALL data is available in the FIFO before we start to
* read from the interconnect.
*
* This credit check is useless when firmware chooses to
* allow multiple outstanding BMI Command Credits, since the next
* credit will already be present. To restrict the Target to one
* BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT.
*
* And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set)
* we cannot wait for the next credit because the Target's FIFO
* will not hold the entire response. So we need the Host to
* start to empty the FIFO sooner. (And again, large reads are
* not used in practice; they are for debug/development only.)
*
* For a more conservative Host implementation (which would be
* safer for a Compact Flash interconnect):
* Set CONSERVATIVE_BMI_READ (above) to 1
* Set HI_OPTION_BMI_CRED_LIMIT and
* reduce BMI_DATASZ_MAX to 32 or 64
*/
if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */
/*
* NB: cmdCredits is declared static for esoteric reasons
* having to do with protection on some OSes.
*/
static A_UINT32 cmdCredits;
A_UINT32 timeout;
cmdCredits = 0;
timeout = BMI_COMMUNICATION_TIMEOUT;
while((!want_timeout || timeout--) && !cmdCredits) {
/* Read the counter register to get the command credits */
address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
/* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing,
* we can read this counter multiple times using a non-incrementing address mode.
* The rationale here is to make all HIF accesses a multiple of 4 bytes */
status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits),
HIF_RD_SYNC_BYTE_FIX, NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
return A_ERROR;
}
/* we did a 4-byte read to the same count register so mask off upper bytes */
cmdCredits &= 0xFF;
}
if (!cmdCredits) {
AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout- bmiBufferReceive no credit\n"));
return A_ERROR;
}
}
#endif
address = mboxAddress[ENDPOINT1];
status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
return A_ERROR;
}
return A_OK;
}
A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer)
{
A_STATUS status;
if (pDev->MailBoxInfo.Flags & HIF_MBOX_FLAG_NO_BUNDLING) {
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HIF requires bundling disabled\n"));
return A_ENOTSUP;
}
status = HIFConfigureDevice(pDev->HIFDevice,
HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
&pDev->HifScatterInfo,
sizeof(pDev->HifScatterInfo));
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
("AR6K: ** HIF layer does not support scatter requests (%d) \n",status));
/* we can try to use a virtual DMA scatter mechanism using legacy HIFReadWrite() */
status = DevSetupVirtualScatterSupport(pDev);
if (A_SUCCESS(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
("AR6K: virtual scatter transfers enabled (max scatter items:%d: maxlen:%d) \n",
DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
}
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
("AR6K: HIF layer supports scatter requests (max scatter items:%d: maxlen:%d) \n",
DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev)));
}
if (A_SUCCESS(status)) {
/* for the recv path, the maximum number of bytes per recv bundle is just limited
* by the maximum transfer size at the HIF layer */
pDev->MaxRecvBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
if (pDev->MailBoxInfo.MboxBusIFType == MBOX_BUS_IF_SPI) {
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6K : SPI bus requires TX bundling disabled\n"));
pDev->MaxSendBundleSize = 0;
} else {
/* for the send path, the max transfer size is limited by the existence and size of
* the extended mailbox address range */
if (pDev->MailBoxInfo.MboxProp[0].ExtendedAddress != 0) {
pDev->MaxSendBundleSize = pDev->MailBoxInfo.MboxProp[0].ExtendedSize;
} else {
/* legacy */
pDev->MaxSendBundleSize = AR6K_LEGACY_MAX_WRITE_LENGTH;
}
if (pDev->MaxSendBundleSize > pDev->HifScatterInfo.MaxTransferSizePerScatterReq) {
/* limit send bundle size to what the HIF can support for scatter requests */
pDev->MaxSendBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq;
}
}
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
("AR6K: max recv: %d max send: %d \n",
DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev), DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)));
}
return status;
}
A_STATUS DevSetup(AR6K_DEVICE *pDev)
{
A_UINT32 blocksizes[AR6K_MAILBOXES];
A_STATUS status = A_OK;
int i;
HTC_CALLBACKS htcCallbacks;
do {
DL_LIST_INIT(&pDev->ScatterReqHead);
/* initialize our free list of IO packets */
INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
A_MUTEX_INIT(&pDev->Lock);
A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
/* the device layer handles these */
htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
htcCallbacks.dsrHandler = DevDsrHandler;
htcCallbacks.context = pDev;
status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks);
if (A_FAILED(status)) {
break;
}
pDev->HifAttached = TRUE;
/* get the addresses for all 4 mailboxes */
status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
&pDev->MailBoxInfo, sizeof(pDev->MailBoxInfo));
if (status != A_OK) {
A_ASSERT(FALSE);
break;
}
/* carve up register I/O packets (these are for ASYNC register I/O ) */
for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
HTC_PACKET *pIOPacket;
pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
pDev,
pDev->RegIOBuffers[i].Buffer,
AR6K_REG_IO_BUFFER_SIZE,
0); /* don't care */
AR6KFreeIOPacket(pDev,pIOPacket);
}
/* get the block sizes */
status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
blocksizes, sizeof(blocksizes));
if (status != A_OK) {
A_ASSERT(FALSE);
break;
}
/* note: we actually get the block size of a mailbox other than 0, for SDIO the block
* size on mailbox 0 is artificially set to 1. So we use the block size that is set
* for the other 3 mailboxes */
pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
/* must be a power of 2 */
A_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
/* assemble mask, used for padding to a block */
pDev->BlockMask = pDev->BlockSize - 1;
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
pDev->BlockSize, pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]));
pDev->GetPendingEventsFunc = NULL;
/* see if the HIF layer implements the get pending events function */
HIFConfigureDevice(pDev->HIFDevice,
HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
&pDev->GetPendingEventsFunc,
sizeof(pDev->GetPendingEventsFunc));
/* assume we can process HIF interrupt events asynchronously */
pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
/* see if the HIF layer overrides this assumption */
HIFConfigureDevice(pDev->HIFDevice,
HIF_DEVICE_GET_IRQ_PROC_MODE,
&pDev->HifIRQProcessingMode,
sizeof(pDev->HifIRQProcessingMode));
switch (pDev->HifIRQProcessingMode) {
case HIF_DEVICE_IRQ_SYNC_ONLY:
AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("HIF Interrupt processing is SYNC ONLY\n"));
/* see if HIF layer wants HTC to yield */
HIFConfigureDevice(pDev->HIFDevice,
HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
&pDev->HifIRQYieldParams,
sizeof(pDev->HifIRQYieldParams));
if (pDev->HifIRQYieldParams.RecvPacketYieldCount > 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
("HIF requests that DSR yield per %d RECV packets \n",
pDev->HifIRQYieldParams.RecvPacketYieldCount));
pDev->DSRCanYield = TRUE;
}
break;
case HIF_DEVICE_IRQ_ASYNC_SYNC:
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
break;
default:
A_ASSERT(FALSE);
}
pDev->HifMaskUmaskRecvEvent = NULL;
/* see if the HIF layer implements the mask/unmask recv events function */
HIFConfigureDevice(pDev->HIFDevice,
HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
&pDev->HifMaskUmaskRecvEvent,
sizeof(pDev->HifMaskUmaskRecvEvent));
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%lX , 0x%lX\n",
(unsigned long)pDev->GetPendingEventsFunc, (unsigned long)pDev->HifMaskUmaskRecvEvent));
status = DevDisableInterrupts(pDev);
if (A_FAILED(status)) {
break;
}
status = DevSetupGMbox(pDev);
} while (FALSE);
if (A_FAILED(status)) {
if (pDev->HifAttached) {
HIFDetachHTC(pDev->HIFDevice);
pDev->HifAttached = FALSE;
}
}
return status;
}
/* here is where the test starts */
A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
{
int i;
A_STATUS status;
int credits = 0;
A_UINT8 params[4];
int numBufs;
int bufferSize;
A_UINT16 temp;
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n"));
do {
/* get the addresses for all 4 mailboxes */
status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
g_MailboxAddrs, sizeof(g_MailboxAddrs));
if (status != A_OK) {
A_ASSERT(FALSE);
break;
}
/* get the block sizes */
status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
g_BlockSizes, sizeof(g_BlockSizes));
if (status != A_OK) {
A_ASSERT(FALSE);
break;
}
/* note, the HIF layer usually reports mbox 0 to have a block size of
* 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
* the same. */
g_BlockSizes[0] = g_BlockSizes[1];
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
g_BlockSizes[1], BUFFER_BLOCK_PAD));
break;
}
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
/* the target lets us know it is ready by giving us 1 credit on
* mailbox 0 */
status = GetCredits(pDev, 0, &credits);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
break;
}
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
/* read the first 4 scratch registers */
status = HIFReadWrite(pDev->HIFDevice,
SCRATCH_ADDRESS,
params,
4,
HIF_RD_SYNC_BYTE_INC,
NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
break;
}
numBufs = params[0];
bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
if ((numBufs * bufferSize) < TOTAL_BYTES) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
TOTAL_BYTES, (numBufs*bufferSize)));
status = A_ERROR;
break;
}
temp = GetEndMarker();
status = HIFReadWrite(pDev->HIFDevice,
SCRATCH_ADDRESS + 4,
(A_UINT8 *)&temp,
2,
HIF_WR_SYNC_BYTE_INC,
NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
break;
}
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
temp = (A_UINT16)g_BlockSizes[1];
/* convert to a mask */
temp = temp - 1;
status = HIFReadWrite(pDev->HIFDevice,
SCRATCH_ADDRESS + 6,
(A_UINT8 *)&temp,
2,
HIF_WR_SYNC_BYTE_INC,
NULL);
if (status != A_OK) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
break;
}
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
/* execute the test on each mailbox */
for (i = 0; i < AR6K_MAILBOXES; i++) {
status = DoOneMboxHWTest(pDev, i);
if (status != A_OK) {
break;
}
}
} while (FALSE);
if (status == A_OK) {
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n"));
} else {
AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n"));
}
/* don't let HTC_Start continue, the target is actually not running any HTC code */
return A_ERROR;
}
/* registered target arrival callback from the HIF layer */
HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo)
{
HTC_TARGET *target = NULL;
A_STATUS status = A_OK;
int i;
A_UINT32 ctrl_bufsz;
A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
printk("HTCCreate !!\n");
do {
/* allocate target memory */
if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL)
{
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
status = A_ERROR;
break;
}
A_MEMZERO(target, sizeof(HTC_TARGET));
A_MUTEX_INIT(&target->HTCLock);
A_MUTEX_INIT(&target->HTCRxLock);
A_MUTEX_INIT(&target->HTCTxLock);
INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
/* give device layer the hif device handle */
target->Device.HIFDevice = hif_handle;
/* give the device layer our context (for event processing)
* the device layer will register it's own context with HIF
* so we need to set this so we can fetch it in the target remove handler */
target->Device.HTCContext = target;
/* set device layer target failure callback */
target->Device.TargetFailureCallback = HTCReportFailure;
/* set device layer recv message pending callback */
target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
target->EpWaitingForBuffers = ENDPOINT_MAX;
A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO));
/* setup device layer */
status = DevSetup(&target->Device);
if (A_FAILED(status)) {
break;
}
/* get the block sizes */
status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
blocksizes, sizeof(blocksizes));
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n"));
break;
}
/* Set the control buffer size based on the block size */
if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH)
{
ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH;
}
else
{
ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH;
}
for (i = 0;i < NUM_CONTROL_BUFFERS;i++)
{
target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz);
if (target->HTCControlBuffers[i].Buffer == NULL) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
status = A_ERROR;
break;
}
}
if (A_FAILED(status)) {
break;
}
/* carve up buffers/packets for control messages */
for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
HTC_PACKET *pControlPacket;
pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
target,
target->HTCControlBuffers[i].Buffer,
ctrl_bufsz,
ENDPOINT_0);
HTC_FREE_CONTROL_RX(target,pControlPacket);
}
for (;i < NUM_CONTROL_BUFFERS;i++) {
HTC_PACKET *pControlPacket;
pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
INIT_HTC_PACKET_INFO(pControlPacket,
target->HTCControlBuffers[i].Buffer,
ctrl_bufsz);
HTC_FREE_CONTROL_TX(target,pControlPacket);
}
} while (FALSE);
if (A_FAILED(status)) {
if (target != NULL) {
HTCCleanup(target);
target = NULL;
}
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n"));
return target;
}
A_STATUS
ar6000_enter_exit_cut_power_state(AR_SOFTC_T *ar, A_BOOL exit)
{
WMI_REPORT_SLEEP_STATE_EVENT wmiSleepEvent ;
A_STATUS status = A_OK;
HIF_DEVICE_POWER_CHANGE_TYPE config;
AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: Cut power %d %d \n", __func__,exit, ar->arWlanPowerState));
#ifdef CONFIG_PM
AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("Wlan OFF %d BT OFf %d \n", ar->arWlanOff, ar->arBTOff));
#endif
do {
if (exit) {
/* Not in cut power state.. exit */
if (ar->arWlanPowerState != WLAN_POWER_STATE_CUT_PWR) {
break;
}
#ifdef TARGET_EUROPA
wlan_setup_power(1,0);
#endif
/* Change the state to ON */
ar->arWlanPowerState = WLAN_POWER_STATE_ON;
/* Indicate POWER_UP to HIF */
config = HIF_DEVICE_POWER_UP;
status = HIFConfigureDevice(ar->arHifDevice,
HIF_DEVICE_POWER_STATE_CHANGE,
&config,
sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
if (status == A_PENDING) {
/* Previously, we decided to wait here until the device becomes fully functional since there is a chance that some entity tries to access the device once we return from the resume callback. However, it was observed that the resume process gets delayed too because of this wait. Commenting it out to speed up the process of resuming */
#if 0
/* Wait for WMI ready event */
A_UINT32 timeleft = wait_event_interruptible_timeout(arEvent,
(ar->arWmiReady == TRUE), wmitimeout * HZ);
if (!timeleft || signal_pending(current)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : Failed to get wmi ready \n"));
status = A_ERROR;
break;
}
#endif
status = A_OK;
} else if (status == A_OK) {
ar6000_exit_cut_power_state(ar);
}
} else {
/* Already in cut power state.. exit */
if (ar->arWlanPowerState == WLAN_POWER_STATE_CUT_PWR) {
break;
}
wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_AWAKE;
ar6000_send_event_to_app(ar, WMI_REPORT_SLEEP_STATE_EVENTID, (A_UINT8*)&wmiSleepEvent, sizeof(WMI_REPORT_SLEEP_STATE_EVENTID));
ar6000_stop_endpoint(ar->arNetDev, TRUE, FALSE);
config = HIF_DEVICE_POWER_CUT;
status = HIFConfigureDevice(ar->arHifDevice,
HIF_DEVICE_POWER_STATE_CHANGE,
&config,
sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
#ifdef TARGET_EUROPA
wlan_setup_power(0,0);
#endif
ar->arWlanPowerState = WLAN_POWER_STATE_CUT_PWR;
}
} while (0);
return status;
}
