int v_setmodefixed(struct v_board_t *board)
{
int iob=board->io_base;
int tmp;
#ifdef SAVEVGA
v_savetextmode(board);
#endif
v1k_softreset(board);
/* switching to native mode */
v_out8(iob+MODEREG, NATIVE_MODE);
/* flipping some bytes */
v_out8(iob+MEMENDIAN, MEMENDIAN_HW);
/* try programming 1024x768@70 in highcolor */
tmp=v_in32(iob+DRAMCTL)&0xdfff; /* reset bit 13 */
v_out32(iob+DRAMCTL, tmp|DEFAULT_WREFRESH);
/* program pixel clock */
if (board->chip == V1000_DEVICE) {
set_PLL(iob, combineNMP(21, 55, 0));
}
else {
tmp = (~0x1800) & v_in32(iob+DRAMCTL);
v_out32(iob+DRAMCTL, tmp);
v_out32(iob+PCLKPLL, v2kcombineNMP(2, 21, 2));
}
usleep(500);
v_initdac(board, 16, 0);
v_out32(iob+CRTCHORZ, HORZ(24, 136, 144, 1024));
v_out32(iob+CRTCVERT, VERT(3, 6, 29, 768));
board->mode.screenwidth=1024;
board->mode.virtualwidth=1024;
board->mode.bitsperpixel=16;
board->mode.fifosize=128;
board->init=1;
v_setframebase(board, 0);
v_out32(iob+CRTCCTL, CTL(0, 0, 0)
|V_PIXFMT_565
|CRTCCTL_VIDEOFIFOSIZE128
|CRTCCTL_HSYNCENABLE
|CRTCCTL_VSYNCENABLE
|CRTCCTL_VIDEOENABLE);
return 0;
}
/* updateWts:
* Iterate over edges in a cell, adjust weights as necessary.
* It always updates the bent edges belonging to a cell.
* A horizontal/vertical edge is updated only if the edge traversed
* is bent, or if it is the traversed edge.
*/
void
updateWts (sgraph* g, cell* cp, sedge* ep)
{
int i;
sedge* e;
int isBend = BEND(g,ep);
int hsz = CHANSZ (cp->bb.UR.y - cp->bb.LL.y);
int vsz = CHANSZ (cp->bb.UR.x - cp->bb.LL.x);
int minsz = MIN(hsz, vsz);
/* Bend edges are added first */
for (i = 0; i < cp->nedges; i++) {
e = cp->edges[i];
if (!BEND(g,e)) break;
updateWt (cp, e, minsz);
}
for (; i < cp->nedges; i++) {
e = cp->edges[i];
if (isBend || (e == ep)) updateWt (cp, e, (HORZ(g,e)?hsz:vsz));
}
}
int v_setmode(struct v_board_t *board, struct v_modeinfo_t *mode)
{
int tmp;
int doubleclock=0;
int M, N, P;
int iob=board->io_base;
/* switching to native mode */
v_out8(iob+MODEREG, NATIVE_MODE|VESA_MODE);
/* flipping some bytes */
/* Must be something better to do than this -- FIX */
switch (mode->bitsperpixel) {
case 32:
v_out8(iob+MEMENDIAN, MEMENDIAN_NO);
break;
case 16:
v_out8(iob+MEMENDIAN, MEMENDIAN_HW);
break;
case 8:
v_out8(iob+MEMENDIAN, MEMENDIAN_END);
break;
}
if (OFLG_ISSET(OPTION_OVERCLOCK_MEM, &vga256InfoRec.options)) {
/* increase Mem/Sys clock to avoid nasty artifacts */
if (board->chip != V1000_DEVICE) {
v_out32(iob+SCLKPLL, 0xa484d); /* mclk=110 sclk=55 */
/* M/N/P/P = 77/5/2/4 */
usleep(500);
}
}
/* this has something to do with memory */
tmp=v_in32(iob+DRAMCTL)&0xdfff; /* reset bit 13 */
v_out32(iob+DRAMCTL, tmp|0x330000);
/* program pixel clock */
if (board->chip == V1000_DEVICE) {
if (110.0 < V1000CalcClock(mode->clock/1000.0, &M, &N, &P)) {
P++;
doubleclock=1;
}
set_PLL(iob, combineNMP(N, M, P));
}
else {
tmp = (~0x1800) & v_in32(iob+DRAMCTL);
v_out32(iob+DRAMCTL, tmp);
V2200CalcClock(mode->clock/1000.0, &M, &N, &P);
v_out32(iob+PCLKPLL, v2kcombineNMP(N, M, P));
}
usleep(500);
/* init the ramdac */
v_initdac(board, mode->bitsperpixel, doubleclock);
v_out32(iob+CRTCHORZ, HORZ(mode->hsyncstart-mode->hdisplay,
mode->hsyncend-mode->hsyncstart,
mode->htotal-mode->hsyncend,
mode->hdisplay));
v_out32(iob+CRTCVERT, VERT(mode->vsyncstart-mode->vdisplay,
mode->vsyncend-mode->vsyncstart,
mode->vtotal-mode->vsyncend,
mode->vdisplay));
/* fill in the mode parameters */
memcpy(&(board->mode), mode, sizeof(struct v_modeinfo_t));
board->mode.fifosize=128;
board->mode.pll_m=M;
board->mode.pll_n=N;
board->mode.pll_p=P;
board->mode.doubleclock=doubleclock;
if (0 == board->mode.virtualwidth)
board->mode.virtualwidth=board->mode.screenwidth;
board->init=1;
v_setframebase(board, 0);
/* Need to fix up syncs */
/* enable the display */
v_out32(iob+CRTCCTL, CTL(0, mode->hsynchi, mode->vsynchi)
|mode->pixelformat
|CRTCCTL_VIDEOFIFOSIZE128
|CRTCCTL_HSYNCENABLE
|CRTCCTL_VSYNCENABLE
|CRTCCTL_VIDEOENABLE);
return 0;
}
