/**
* initializes the AD conversion module.
*/
void AD_init (void)
{
OutFlgA = FALSE; /* No measured value */
ad_ModeFlgA = IDLE; /* Device isn't running */
setReg(ADCA_ADCR1, 0x4800); /* Set control register 1 */
setReg(ADCA_ADOFS0, 0); /* Set offset reg. 0 */
setReg(ADCA_ADOFS1, 0); /* Set offset reg. 1 */
setReg(ADCA_ADOFS2, 0); /* Set offset reg. 2 */
setReg(ADCA_ADHLMT0, 0x7ff8); /* Set high limit reg. 0 */
setReg(ADCA_ADHLMT1, 0x7ff8); /* Set high limit reg. 1 */
setReg(ADCA_ADHLMT2, 0x7ff8); /* Set high limit reg. 2 */
setReg(ADCA_ADLLMT0, 0); /* Set low limit reg. 0 */
setReg(ADCA_ADLLMT1, 0); /* Set low limit reg. 1 */
setReg(ADCA_ADLLMT2, 0); /* Set low limit reg. 2 */
setReg(ADCA_ADZCSTAT, 0xff); /* Clear zero crossing status flags */
setReg(ADCA_ADLSTAT, 0xffff); /* Clear high and low limit status */
setReg(ADCA_ADSTAT, 0x800); /* Clear EOSI flag */
setReg(ADCA_ADSDIS, 0xf8); /* Enable/disable of samples */
setReg(ADCA_ADLST1, 0x105); /* Set ADC channel list reg. */
setReg(ADCA_ADZCC, 0); /* Set zero crossing control reg. */
setReg(ADCA_ADCR2, 0xf); /* Set prescaler */
_sample_A[0] = 0;
_sample_A[1] = 0;
_sample_A[2] = 0;
HWEnDiA();
OutFlgB = FALSE; /* No measured value */
ad_ModeFlgB = IDLE; /* Device isn't running */
setReg(ADCB_ADCR1, 0x4800); /* Set control register 1 */
setReg(ADCB_ADOFS0, 0); /* Set offset reg. 0 */
setReg(ADCB_ADOFS1, 0); /* Set offset reg. 1 */
setReg(ADCB_ADOFS2, 0); /* Set offset reg. 2 */
setReg(ADCB_ADHLMT0, 0x7ff8); /* Set high limit reg. 0 */
setReg(ADCB_ADHLMT1, 0x7ff8); /* Set high limit reg. 1 */
setReg(ADCB_ADHLMT2, 0x7ff8); /* Set high limit reg. 2 */
setReg(ADCB_ADLLMT0, 0); /* Set low limit reg. 0 */
setReg(ADCB_ADLLMT1, 0); /* Set low limit reg. 1 */
setReg(ADCB_ADLLMT2, 0); /* Set low limit reg. 2 */
setReg(ADCB_ADZCSTAT, 0xff); /* Clear zero crossing status flags */
setReg(ADCB_ADLSTAT, 0xffff); /* Clear high and low limit status */
setReg(ADCB_ADSTAT, 0x800); /* Clear EOSI flag */
setReg(ADCB_ADSDIS, 0xf8); /* Enable/disable of samples */
setReg(ADCB_ADLST1, 0x105); /* Set ADC channel list reg. */
setReg(ADCB_ADZCC, 0); /* Set zero crossing control reg. */
setReg(ADCB_ADCR2, 0xf); /* Set prescaler */
_sample_B[0] = 0;
_sample_B[1] = 0;
_sample_B[2] = 0;
HWEnDiB();
}
/*
* enables triggered sequential mode synchronous with the
* PWM generation signal.
*/
byte AD_enableIntTriggerB(void)
{
if (ad_ModeFlgB != IDLE) /* Is the device in running mode? */
return ERR_BUSY;
/// starts sampling in triggered sequential mode
/// synchro with PWM generation.
setRegBits (ADCB_ADCR1, 0x04);
clrRegBits (ADCB_ADCR1, 0x03);
ad_ModeFlgB = MEASURE; /* Set state of device to the measure mode */
HWEnDiB();
return ERR_OK;
}
/**
* This method performs one measurement on channel B
*
* @param wait waits for result to be ready.
* @return ERR_OK after a successful sampling, ERR_BUSY if the device is
* already running a conversion.
*
**************************************************************************************/
byte AD_measureB(bool wait)
{
if (ad_ModeFlgB != IDLE)
return ERR_BUSY;
/* sequential once mode */
clrRegBits (ADCB_ADCR1, 0x00);
ad_ModeFlgB = MEASURE;
HWEnDiB();
/* wait on the interrupt */
if (wait)
while (ad_ModeFlgB == MEASURE) {}
return ERR_OK;
}
/**
* initializes the AD conversion module.
*
**************************************************************************************/
void AD_init (void)
{
TIC_init (); /*ADC interrupt syncronized with PWM */
OutFlgA = FALSE; /* No measured value */
ad_ModeFlgA = IDLE; /* Device isn't running */
setReg(ADCA_ADCR1, 0x4800); /* Set control register 1 */
setReg(ADCA_ADOFS0, 0); /* Set offset reg. 0 */
setReg(ADCA_ADOFS1, 0); /* Set offset reg. 1 */
setReg(ADCA_ADOFS2, 0); /* Set offset reg. 2 */
setReg(ADCA_ADOFS3, 0); /* Set offset reg. 3 */
setReg(ADCA_ADOFS4, 0); /* Set offset reg. 4 */
setReg(ADCA_ADOFS5, 0); /* Set offset reg. 5 */
setReg(ADCA_ADOFS6, 0); /* Set offset reg. 6 */
setReg(ADCA_ADOFS7, 0); /* Set offset reg. 7 */
setReg(ADCA_ADHLMT0, 0x7ff8); /* Set high limit reg. 0 */
setReg(ADCA_ADHLMT1, 0x7ff8); /* Set high limit reg. 1 */
setReg(ADCA_ADHLMT2, 0x7ff8); /* Set high limit reg. 2 */
setReg(ADCA_ADHLMT3, 0x7ff8); /* Set high limit reg. 3 */
setReg(ADCA_ADHLMT4, 0x7ff8); /* Set high limit reg. 4 */
setReg(ADCA_ADHLMT5, 0x7ff8); /* Set high limit reg. 5 */
setReg(ADCA_ADHLMT6, 0x7ff8); /* Set high limit reg. 6 */
setReg(ADCA_ADHLMT7, 0x7ff8); /* Set high limit reg. 7 */
setReg(ADCA_ADLLMT0, 0); /* Set low limit reg. 0 */
setReg(ADCA_ADLLMT1, 0); /* Set low limit reg. 1 */
setReg(ADCA_ADLLMT2, 0); /* Set low limit reg. 2 */
setReg(ADCA_ADLLMT3, 0); /* Set low limit reg. 0 */
setReg(ADCA_ADLLMT4, 0); /* Set low limit reg. 1 */
setReg(ADCA_ADLLMT5, 0); /* Set low limit reg. 2 */
setReg(ADCA_ADLLMT6, 0); /* Set low limit reg. 0 */
setReg(ADCA_ADLLMT7, 0); /* Set low limit reg. 1 */
setReg(ADCA_ADZCSTAT, 0xffff); /* Clear zero crossing status flags */
setReg(ADCA_ADLSTAT, 0xffff); /* Clear high and low limit status */
setReg(ADCA_ADSTAT, 0x0800); /* Clear EOSI flag */
setReg(ADCA_ADSDIS, 0x0); /* Enable/disable of samples */
// setReg(ADCA_ADLST1, 0x12816); /* Set ADC channel list reg. */
// setReg(ADCA_ADLST1, 0x30292); /* Set ADC channel list reg. */
setReg(ADCA_ADZCC, 0); /* Set zero crossing control reg. */
setReg(ADCA_ADCR2, 0x3); /* Set prescaler */
_sample_A[0] = 15;
_sample_A[1] = 15;
_sample_A[2] = 15;
_sample_A[3] = 15;
_sample_A[4] = 15;
_sample_A[5] = 15;
_sample_A[6] = 15;
_sample_A[7] = 15;
HWEnDiA();
OutFlgB = FALSE; /* No measured value */
ad_ModeFlgB = IDLE; /* Device isn't running */
setReg(ADCB_ADCR1, 0x4800); /* Set control register 1 */
setReg(ADCB_ADOFS0, 0); /* Set offset reg. 0 */
setReg(ADCB_ADOFS1, 0); /* Set offset reg. 1 */
setReg(ADCB_ADOFS2, 0); /* Set offset reg. 2 */
setReg(ADCB_ADOFS3, 0); /* Set offset reg. 3 */
setReg(ADCB_ADOFS4, 0); /* Set offset reg. 4 */
setReg(ADCB_ADOFS5, 0); /* Set offset reg. 5 */
setReg(ADCB_ADOFS6, 0); /* Set offset reg. 6 */
setReg(ADCB_ADOFS7, 0); /* Set offset reg. 7 */
setReg(ADCB_ADHLMT0, 0x7ff8); /* Set high limit reg. 0 */
setReg(ADCB_ADHLMT1, 0x7ff8); /* Set high limit reg. 1 */
setReg(ADCB_ADHLMT2, 0x7ff8); /* Set high limit reg. 2 */
setReg(ADCB_ADHLMT3, 0x7ff8); /* Set high limit reg. 3 */
setReg(ADCB_ADHLMT4, 0x7ff8); /* Set high limit reg. 4 */
setReg(ADCB_ADHLMT5, 0x7ff8); /* Set high limit reg. 5 */
setReg(ADCB_ADHLMT6, 0x7ff8); /* Set high limit reg. 6 */
setReg(ADCB_ADHLMT7, 0x7ff8); /* Set high limit reg. 7 */
setReg(ADCB_ADLLMT0, 0); /* Set low limit reg. 0 */
setReg(ADCB_ADLLMT1, 0); /* Set low limit reg. 1 */
setReg(ADCB_ADLLMT2, 0); /* Set low limit reg. 2 */
setReg(ADCB_ADLLMT3, 0); /* Set low limit reg. 0 */
setReg(ADCB_ADLLMT4, 0); /* Set low limit reg. 1 */
setReg(ADCB_ADLLMT5, 0); /* Set low limit reg. 2 */
setReg(ADCB_ADLLMT6, 0); /* Set low limit reg. 0 */
setReg(ADCB_ADLLMT7, 0); /* Set low limit reg. 1 */
setReg(ADCB_ADZCSTAT, 0xffff); /* Clear zero crossing status flags */
setReg(ADCB_ADLSTAT, 0xffff); /* Clear high and low limit status */
setReg(ADCB_ADSTAT, 0x0800); /* Clear EOSI flag */
setReg(ADCB_ADSDIS, 0x0); /* Enable/disable of samples */
// setReg(ADCB_ADLST1, 0x12816); /* Set ADC channel list reg. */
// setReg(ADCB_ADLST1, 0x30292); /* Set ADC channel list reg. */
setReg(ADCB_ADZCC, 0); /* Set zero crossing control reg. */
setReg(ADCB_ADCR2, 0x3); /* Set prescaler */
_sample_B[0] = 15;
_sample_B[1] = 15;
_sample_B[2] = 15;
_sample_B[3] = 15;
_sample_B[4] = 15;
_sample_B[5] = 15;
_sample_B[6] = 15;
_sample_B[7] = 15;
HWEnDiB();
}