static void __init mx28_init_l2switch(void) { struct platform_device *pdev; struct switch_platform_data *pswitch; struct fec_platform_data *pfec; u32 val; __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); while (BM_OCOTP_CTRL_BUSY & __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) udelay(10); pdev = mxs_get_device("mxs-l2switch", 0); if (pdev == NULL || IS_ERR(pdev)) return; val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CUSTn(pdev->id)); pdev->resource = l2switch_resources; pdev->num_resources = ARRAY_SIZE(l2switch_resources); pdev->dev.platform_data = &l2switch_data; pswitch = (struct switch_platform_data *)pdev->dev.platform_data; pfec = pswitch->fec_enet; pfec->mac[0] = 0x00; pfec->mac[1] = 0x04; pfec->mac[2] = (val >> 24) & 0xFF; pfec->mac[3] = (val >> 16) & 0xFF; pfec->mac[4] = (val >> 8) & 0xFF; pfec->mac[5] = (val >> 0) & 0xFF; mxs_add_device(pdev, 2); }
static void __init mx28_init_fec(void) { struct platform_device *pdev; struct mxs_dev_lookup *lookup; struct fec_platform_data *pfec; int i; u32 val; __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); while (BM_OCOTP_CTRL_BUSY & __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) udelay(10); lookup = mxs_get_devices("mxs-fec"); if (lookup == NULL || IS_ERR(lookup)) return; for (i = 0; i < lookup->size; i++) { pdev = lookup->pdev + i; val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CUSTn(pdev->id)); switch (pdev->id) { case 0: pdev->resource = fec0_resource; pdev->num_resources = ARRAY_SIZE(fec0_resource); pdev->dev.platform_data = &fec_pdata0; break; case 1: pdev->resource = fec1_resource; pdev->num_resources = ARRAY_SIZE(fec1_resource); pdev->dev.platform_data = &fec_pdata1; break; default: return; } pfec = (struct fec_platform_data *)pdev->dev.platform_data; pfec->mac[0] = 0x00; pfec->mac[1] = 0x04; pfec->mac[2] = (val >> 24) & 0xFF; pfec->mac[3] = (val >> 16) & 0xFF; pfec->mac[4] = (val >> 8) & 0xFF; pfec->mac[5] = (val >> 0) & 0xFF; mxs_add_device(pdev, 2); } }
static int fuse_read_addr(u32 addr, u32 *pdata) { u32 ctrl_reg = 0; #ifdef CONFIG_IMX_OTP_READ_SHADOW_REG *pdata = readl(IMX_OTP_BASE + HW_OCOTP_CUSTn(addr)); printf("Shadow register data: 0x%X\n", *pdata); #endif ctrl_reg = readl(IMX_OTP_BASE + HW_OCOTP_CTRL); ctrl_reg &= ~BM_OCOTP_CTRL_ADDR; ctrl_reg &= ~BM_OCOTP_CTRL_WR_UNLOCK; ctrl_reg |= BF(addr, OCOTP_CTRL_ADDR); writel(ctrl_reg, IMX_OTP_BASE + HW_OCOTP_CTRL); writel(BM_OCOTP_READ_CTRL_READ_FUSE, IMX_OTP_BASE + HW_OCOTP_READ_CTRL); if (otp_wait_busy(0)) return -1; *pdata = readl(IMX_OTP_BASE + HW_OCOTP_READ_FUSE_DATA); *pdata = BF_OCOTP_READ_FUSE_DATA_DATA(*pdata); return 0; }