/*
* ======== hwiPostInit ========
* Function to be called during module startup to complete the
* initialization of any statically created or constructed Hwi.
* returns (0) and clean 'eb' on success
* returns 'eb' *and* 'n' for number of successful createFxn() calls iff
* one of the createFxn() calls fails
*/
static Int hwiPostInit (Hwi_Object *hwi, Error_Block *eb)
{
Int i;
#ifndef ti_sysbios_hal_Hwi_DISABLE_ALL_HOOKS
for (i = 0; i < Hwi_hooks.length; i++) {
hwi->hookEnv[i] = (Ptr)0;
if (Hwi_hooks.elem[i].createFxn != NULL) {
Hwi_hooks.elem[i].createFxn((IHwi_Handle)hwi, eb);
if (Error_check(eb)) {
return (i);
}
}
}
#endif
Hwi_setPriority(hwi->intNum, hwi->priority);
Hwi_setType(hwi->intNum, hwi->type);
if (hwi->type == Hwi_Type_IRQ) {
Hwi_plug(hwi->intNum, Hwi_dispatchIRQ);
}
else {
Hwi_plug(hwi->intNum, (Hwi_PlugFuncPtr)(hwi->fxn));
}
return (0);
}
/*
* ======== Hwi_reconfig ========
* Reconfigure a dispatched interrupt.
*/
Void Hwi_reconfig(Hwi_Object *hwi, Hwi_FuncPtr fxn, const Hwi_Params *params)
{
UInt intNum;
for (intNum = 0; intNum < Hwi_NUM_INTERRUPTS; intNum++) {
if (Hwi_module->dispatchTable[intNum] == hwi) {
break;
}
}
Hwi_disableInterrupt(intNum);
hwi->fxn = fxn;
hwi->arg = params->arg;
hwi->sense = params->sense;
hwi->type = params->type;
hwi->priority = params->priority;
Hwi_setSense(intNum, hwi->sense);
Hwi_setType(intNum, hwi->type);
Hwi_setPriority(intNum, hwi->priority);
if (params->enableInt) {
Hwi_enableInterrupt(intNum);
}
}
static Void initIntController()
{
UInt i;
/*
* The interrupt controller has no RESET feature and
* none would be required after a hard reset or power up.
* But the CCS reset/reload process doesn't do a hard reset.
* The code below tries to "virtually" reset the intc.
*/
/*
* Force all interrupts to be IRQ
*/
Hwi_vim.FIRQPR[0] = 0;
Hwi_vim.FIRQPR[1] = 0;
/*
* Configure the interrupt priority (and therefore type)
*/
for (i = 0; i < Hwi_NUM_INTERRUPTS; i++) {
if (Hwi_module->dispatchTable[i] == NULL) {
Hwi_setPriority(i, i);
}
else {
Hwi_setPriority(i, Hwi_module->dispatchTable[i]->priority);
}
}
/* clear all enables */
Hwi_vim.REQENACLR[0] = 0xffffffff;
Hwi_vim.REQENACLR[1] = 0xffffffff;
Hwi_vim.WAKEENACLR[0] = 0xffffffff;
Hwi_vim.WAKEENACLR[1] = 0xffffffff;
/* init per REQENASET settings */
Hwi_vim.REQENASET[0] = Hwi_module->req0Mask;
Hwi_vim.REQENASET[1] = Hwi_module->req1Mask;
}
/*
* ======== Hwi_reconfig ========
* Reconfigure a dispatched interrupt.
*/
Void Hwi_reconfig(Hwi_Object *hwi, Hwi_FuncPtr fxn, const Hwi_Params *params)
{
UInt intNum;
Int priority;
for (intNum = 0; intNum < Hwi_NUM_INTERRUPTS; intNum++) {
if (Hwi_module->dispatchTable[intNum] == hwi) {
break;
}
}
Hwi_disableInterrupt(intNum);
hwi->fxn = fxn;
hwi->arg = params->arg;
priority = params->priority;
/*
* the -1 sentinel priority is the default passed by hal Hwi_create().
* Translate it to 31, which is our default priority.
*/
if (priority == -1) {
priority = 31;
}
Hwi_module->priorities[intNum] = priority;
Hwi_setPriority(intNum, priority);
Assert_isTrue((params->maskSetting != Hwi_MaskingOption_BITMASK),
Hwi_A_unsupportedMaskingOption);
switch (params->maskSetting) {
case Hwi_MaskingOption_NONE:
hwi->handler = Hwi_handlerNONE;
break;
case Hwi_MaskingOption_ALL:
hwi->handler = Hwi_handlerALL;
break;
case Hwi_MaskingOption_LOWER:
hwi->handler = Hwi_handlerLOWER;
break;
case Hwi_MaskingOption_BITMASK:
case Hwi_MaskingOption_SELF:
hwi->handler = Hwi_handlerSELF;
break;
}
if (params->enableInt) {
Hwi_enableInterrupt(intNum);
}
}
static Void initIntControllers()
{
UInt i;
Hwi_l2Intc.OCP_CFG |= 2; /* reset L2 Interrupt Controller */
/*
* The L1 interrupt controller has no RESET feature and
* none would be required after a hard reset or power up.
* But the CCS reset/reload process doesn't do a hard reset.
* The code below tries to "virtually" reset the L1 intc.
*/
Hwi_l1Intc.MIR = 0xffffffff;/* mask all interrupts */
Hwi_l1Intc.ITR = 0; /* clear any pending interrupts */
Hwi_l1Intc.CONTROL = 0x3; /* latch any latent interrupts */
Hwi_l1Intc.ITR = 0; /* drown the ashes */
Hwi_l1Intc.CONTROL = 0x3; /* stir the ashes */
Hwi_l1Intc.ITR = 0; /* and drown them again */
/*
* Set configured interrupt Sense and Priority for each
* L1 and L2 interrupt
*/
for (i=0; i<96; i++) {
if ((Hwi_module->dispatchTable[i] == NULL) ||
(Hwi_module->dispatchTable[i]->sense == Hwi_Sense_TRM)) {
if (i < 32 ) {
Hwi_setSense(i, (l1DefaultSenseTable[i/8] &
(1 << (i%8))) ?
Hwi_Sense_LEVEL : Hwi_Sense_EDGE);
}
else {
Hwi_setSense(i, (l2DefaultSenseTable[(i-32)/8] &
(1 << ((i-32)%8))) ?
Hwi_Sense_LEVEL : Hwi_Sense_EDGE);
}
}
else {
Hwi_setSense(i, Hwi_module->dispatchTable[i]->sense);
Hwi_setPriority(i, Hwi_module->dispatchTable[i]->priority);
Hwi_setType(i, Hwi_module->dispatchTable[i]->type);
}
}
/* Route L2 FIQ to FIQ */
Hwi_setType(2, Hwi_Type_FIQ);
}
static Void initIntController()
{
UInt i;
/*
* Issue a hard reset to the INTC through the psc.
* TBD!
*/
/*
* Set priority hold mode, auto-individual-nesting,
* and normal-wakeup modes.
*/
Hwi_cpIntc.CR = 0x14;
/* Disable all interrupts to start with */
Hwi_cpIntc.ECR[0] = 0xffffffff;
Hwi_cpIntc.ECR[1] = 0xffffffff;
Hwi_cpIntc.ECR[2] = 0xffffffff;
Hwi_cpIntc.ECR[3] = 0xffffffff;
/* Enable any statically config'd interrupts that are enabled */
Hwi_cpIntc.ESR[0] = Hwi_module->er[0];
Hwi_cpIntc.ESR[1] = Hwi_module->er[1];
Hwi_cpIntc.ESR[2] = Hwi_module->er[2];
Hwi_cpIntc.ESR[3] = Hwi_module->er[3];
/* Clear any currently pending, enabled interrupts */
Hwi_cpIntc.SECR[0] = Hwi_module->er[0];
Hwi_cpIntc.SECR[1] = Hwi_module->er[1];
Hwi_cpIntc.SECR[2] = Hwi_module->er[2];
Hwi_cpIntc.SECR[3] = Hwi_module->er[3];
/* Set interrupt priorities */
for (i = 0; i < Hwi_NUM_INTERRUPTS; i++) {
Hwi_setPriority(i, Hwi_module->priorities[i]);
}
/*
* Channel mapping/priorities are hard wired, no need to
* configure the Channel Map Registers.
*/
/*
* Set up vector table.
* The vectorizer is used as a power assist to calculate
* the address of the dispatch table entry.
*/
/* Point Vector Base to generated Hwi_vectorTable */
Hwi_cpIntc.VBR = Hwi_module->vectorTableBase;
/* each entry is 8 bytes */
Hwi_cpIntc.VSR = 1;
/* init spurious interrupt vector */
Hwi_cpIntc.VNR = Hwi_spuriousInt;
/*
* Enable each host interrupt (FIQ and IRQ)
*/
Hwi_cpIntc.HIEISR = 0; /* enable FIQ */
Hwi_cpIntc.HIEISR = 1; /* enable IRQ */
/*
* Globally enable all host interrupts
*/
Hwi_cpIntc.GER = 1;
}
/*
* ======== Hwi_initIntController ========
*/
Void Hwi_initIntController()
{
UInt32 i, j;
UInt32 intActiveReg;
/*
* Disable IRQs
*/
Hwi_disable();
/*
* Disable forwarding of interrupts in GIC Distributer and CPU interface
* Controller.
*/
Hwi_gicd.CTLR = 0x0;
Hwi_gicc.CTLR = 0x0;
/*
* Disable all interrupts at startup
*/
for (i = 0; i < NUM_GICD_ENABLE_REGS; i++) {
/*
* Disable the forwarding of the corresponding interrupt from GIC
* distributor to CPU interface.
*/
Hwi_gicd.ICENABLER[i] = 0xFFFFFFFF;
/* Track interrupts that cannot be disabled */
Hwi_module->iser[i] |= Hwi_gicd.ISENABLER[i];
}
/*
* Enable forwarding of interrupts in GIC Distributor and CPU interface
* Controller.
*/
Hwi_gicd.CTLR = 0x1;
Hwi_gicc.CTLR = 0x1;
/* Search for any previously active interrupts and acknowledge them */
for (i = 0; i < NUM_GICD_ENABLE_REGS; i++) {
intActiveReg = Hwi_gicd.ISACTIVER[i];
if (intActiveReg) {
for (j = 0; j < 32; j++) {
if (intActiveReg & 0x1) {
Hwi_gicc.EOIR = i*32 + j;
}
intActiveReg = intActiveReg >> 1;
}
}
}
/*
* Clear any currently pending enabled interrupts
*
* Note: SGIs are always enabled
*/
for (i = 0; i < 4; i++) {
Hwi_gicd.CPENDSGIR[i] = 0x01010101;
}
for (i = 0; i < NUM_GICD_ENABLE_REGS; i++) {
Hwi_gicd.ICPENDR[i] = 0xFFFFFFFF;
}
/*
* Clear all interrupt active status registers
*/
for (i = 0; i < NUM_GICD_ENABLE_REGS; i++) {
Hwi_gicd.ICACTIVER[i] = 0xFFFFFFFF;
}
/*
* Enable any statically config'd interrupts that are enabled.
*/
for (i = 0; i < NUM_GICD_ENABLE_REGS; i++) {
Hwi_gicd.ISENABLER[i] = Hwi_module->iser[i];
}
/*
* Set MPU0 as the target processor for all interrupts.
*
* ITARGETSR[0:7] are Read-Only
*/
for (i = 8; i < (Hwi_NUM_INTERRUPTS / 4); i++) {
Hwi_gicd.ITARGETSR[i] = Hwi_module->itargetsr[i];
}
/*
* Initialize Binary Point Register
*/
Hwi_gicc.BPR = Hwi_BPR;
/*
* Set configured interrupt Sense and Priority for each
* interrupt
*/
for (i=0; i < Hwi_NUM_INTERRUPTS; i++) {
Hwi_setPriority(i, Hwi_module->dispatchTable[i]->priority);
}
/*
* Initialize Interrupt Priority Mask Register
*
* Initialize PMR with the minimum possible interrupt priority.
*/
Hwi_gicc.PMR = Hwi_MIN_INT_PRIORITY;
/*
* Set trigger sensitivity of interrupts
*
* On the Cortex-A15:
* - For SGI: The ICFGR bits are read-only and a bit-pair always
* reads as b10 because SGIs are edge-triggered.
* - For PPI: The ICFGR bits are read-only and a bit-pair always
* reads as b01 because PPIs are level-sensitive.
* - For SPI: The LSB of the bit-pair is read only and is always
* 1. MSB can be altered to change trigger sensitivity.
* b01 Interrupt is active-High level-sensitive
* b11 Interrupt is rising edge-sensitive
*/
for (i = 2; i < (Hwi_NUM_INTERRUPTS / 16); i++) {
Hwi_gicd.ICFGR[i] = Hwi_module->icfgr[i];
}
}
