/******************************************************************************
** INTERNAL FUNCTION DEFINITIONS
*******************************************************************************/
int main(void)
{
#ifndef _TMS320C6X
unsigned int index;
#endif
/* Setting the Master priority for the VPIF and LCD DMA controllers to highest level */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI1) &= 0x00FFFFFF;
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI2) &= 0x0FFFFFFF;
#ifdef _TMS320C6X
/* Set MAR bits and configure L1 cache */
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x10000000);
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K );
#else
/* Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memeory range and set
* the atributes for the same. The DDR memory range is from 0xC0000000
* to 0xCFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xCFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions */
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xD00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/* Configures translation table base register
* with pagetable base address. */
CP15TtbSet((unsigned int )pageTable);
/* Enables MMU */
CP15MMUEnable();
/* Enable Instruction Cache */
CP15ICacheEnable();
/* Enable Data Cache */
CP15DCacheEnable();
#endif
/* Allocate pointers to buffers */
buff_luma[0] = buff_luma1;
buff_luma[1] = buff_luma2;
buff_chroma[0] = buff_chroma1;
buff_chroma[1] = buff_chroma2;
/* Initializing palette for first buffer */
Rgb_buffer1[0] = 0x4000;
for (i = 1; i < 16; i++)
Rgb_buffer1[i] = 0x0000;
videoTopRgb1 = Rgb_buffer1 + i;
/* Initializing palette for second buffer */
Rgb_buffer2[0] = 0x4000;
for (i = 1; i < 16; i++)
Rgb_buffer2[i] = 0x0000;
videoTopRgb2 = Rgb_buffer2 + i;
/* Power on VPIF */
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_VPIF, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
/* Initializing ARM/DSP INTC */
SetupIntc();
/* Initialize I2C and program UI GPIO expander, TVP5147, and ADV7343 via I2C */
I2CPinMuxSetup(0);
/* enable video via gpio expander to ensure we have exclusive access to the bus */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C, I2C_SLAVE_UI_EXPANDER);
I2CGPIOInit(SOC_I2C_0_REGS);
I2CGPIOSetOutput(SOC_I2C_0_REGS);
/*Initialize the TVP5147 to accept composite video */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C,
I2C_SLAVE_CODEC_TVP5147_2_COMPOSITE);
TVP5147CompositeInit(SOC_I2C_0_REGS);
/* Setup VPIF pinmux */
VPIFPinMuxSetup();
/* Setup LCD */
SetUpLCD();
/* Initialize VPIF */
SetUpVPIFRx();
VPIFDMARequestSizeConfig(SOC_VPIF_0_REGS, VPIF_REQSIZE_ONE_TWENTY_EIGHT);
VPIFEmulationControlSet(SOC_VPIF_0_REGS, VPIF_HALT);
/* Initialize buffer addresses for 1st frame*/
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) buff_luma[0], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_CHROMA, (unsigned int) buff_chroma[0], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_LUMA, (unsigned int) (buff_luma[0] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_CHROMA, (unsigned int) (buff_chroma[0] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
/* configuring the base ceiling */
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0);
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1);
/* Enable capture */
VPIFCaptureChanenEnable(SOC_VPIF_0_REGS, VPIF_CHANNEL_0);
/* Enable VPIF interrupt */
VPIFInterruptEnable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
VPIFInterruptEnableSet(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
/* enable End of frame interrupt */
RasterEndOfFrameIntEnable(SOC_LCDC_0_REGS);
/* enable raster */
RasterEnable(SOC_LCDC_0_REGS);
buffcount++;
buffcount2 = buffcount - 1;
/* Run forever */
while (1)
{
/* Wait here till a new frame is not captured */
while (!captured);
/* Process the next buffer only when both the raster buffers
* are pointing to the current buffer to avoid jitter effect */
if (updated == 3)
{
processed = 0;
changed = 0;
updated = 0;
/* Convert the buffer from CBCR422 semi-planar to RGB565,
* Flush and invalidate the processed buffer so that the DMA reads the processed data,
* set the flag for the buffer to be displayed on the LCD (which would be the processed buffer)
* and notify the LCD of availability of a processed buffer.
* The output buffers are ping-ponged each time. */
if (pingpong)
{
cbcr422sp_to_rgb565_c(
(const unsigned char *) (videoTopC + OFFSET),
DISPLAY_IMAGE_HEIGHT, CAPTURE_IMAGE_WIDTH, ccCoeff,
(const unsigned char *) (videoTopY + OFFSET),
CAPTURE_IMAGE_WIDTH, videoTopRgb1, DISPLAY_IMAGE_WIDTH, DISPLAY_IMAGE_WIDTH);
#ifdef _TMS320C6X
CacheWBInv((unsigned int) videoTopRgb1, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#else
CP15DCacheCleanBuff((unsigned int) videoTopRgb1,DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#endif
display_buff_1 = 1;
changed = 1;
}
else
{
cbcr422sp_to_rgb565_c(
(const unsigned char *) (videoTopC + OFFSET),
DISPLAY_IMAGE_HEIGHT, CAPTURE_IMAGE_WIDTH, ccCoeff,
(const unsigned char *) (videoTopY + OFFSET),
CAPTURE_IMAGE_WIDTH, videoTopRgb2, DISPLAY_IMAGE_WIDTH, DISPLAY_IMAGE_WIDTH);
#ifdef _TMS320C6X
CacheWBInv((unsigned int) videoTopRgb2, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#else
CP15DCacheCleanBuff((unsigned int) videoTopRgb2, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#endif
display_buff_1 = 0;
changed = 1;
}
pingpong = !pingpong;
captured = 0;
processed = 1;
}
}
}
bool I2C::Init()
{
I2C_InitTypeDef I2C_InitStructure;
#ifdef I2C_USE_DMA
DMA_InitTypeDef DMA_InitStructure;
uint8_t dmaTxIrq,dmaRxIrq;
#endif
NVIC_InitTypeDef NVIC_InitStructure;
uint8_t eventIrq,errorIrq;
uint32_t i2cClk;//i2c clock
uint16_t sclPin,sdaPin;
if(this->GetI2CNumber()==1)//i2c1
{
#ifdef USE_I2C1
i2cClk=RCC_APB1Periph_I2C1;//i2 clock setting
eventIrq=I2C1_EV_IRQn;
errorIrq=I2C1_ER_IRQn;
#ifdef I2C_USE_DMA
if(mUseDma)
{
dmaTxIrq=DMA1_Channel6_IRQn;
dmaRxIrq=DMA1_Channel7_IRQn;
}
#endif
if(mRemap)//remap gpio pin
{
sclPin=GPIO_Pin_8;
sdaPin=GPIO_Pin_9;
}
else
{
sclPin=GPIO_Pin_6;
sdaPin=GPIO_Pin_7;
}
#endif
}
else
{
#ifdef USE_I2C2
i2cClk=RCC_APB1Periph_I2C2;
sclPin=GPIO_Pin_10;
sdaPin=GPIO_Pin_11;
eventIrq=I2C2_EV_IRQn;
errorIrq=I2C2_ER_IRQn;
#ifdef I2C_USE_DMA
if(mUseDma)
{
dmaTxIrq=DMA1_Channel4_IRQn;
dmaRxIrq=DMA1_Channel5_IRQn;
}
#endif
pI2C2=this;
#endif
}
Soft_Reset();//清空I2C相关寄存器 //重要，不能删除
////设置成默认值
mI2C->CR1 &= ~I2C_CR1_PE;//I2C失能 I2C_Cmd(I2C,DISABLE); //失能 I2C
// I2CGPIODeInit(sclPin,sdaPin);//IO设置成默认值
//
// RCC_APB1PeriphResetCmd(i2cClk,ENABLE);//重置clk时钟 防止有错误标志 // I2C_DeInit(I2C); //将IIC端口初始化，否则GPIO不能被操作
// RCC_APB1PeriphResetCmd(i2cClk,DISABLE);//关闭clk重置
// RCC_APB1PeriphClockCmd(i2cClk,DISABLE);//关闭CLK时钟
#ifdef I2C_USE_DMA
if(mUseDma)
{
//dma默认值 重要，不能去掉，不然在硬件连接有错时可能会导致DMA无法恢复，以致不能使用DMA发送数据
DMA_DeInit(mDmaTxChannel);
DMA_DeInit(mDmaRxChannel);
}
#endif
/////初始化
//I2C CLK初始化
RCC_APB1PeriphResetCmd(i2cClk,ENABLE);//重置clk时钟 防止有错误标志
RCC_APB1PeriphResetCmd(i2cClk,DISABLE);//关闭clk重置
RCC_APB1PeriphClockCmd(i2cClk,ENABLE);//开启I2C时钟
if(!I2C_CHACK_BUSY_FIX(i2cClk,sclPin,sdaPin))//检测总线是否被从机拉低（SDA为低）（一般是因为传送过程中出错导致无法一直处于busy状态）
{
mState=STATE_ERROR;
return 0;
}
I2CGPIOInit(sclPin,sdaPin);
//i2c使能 I2C_Cmd(I2C,ENABLE);
//mI2C->CR1 |= I2C_CR1_PE;//由于在下面I2C_Init()函数中会开启，所以这里屏蔽了
#ifdef I2C_USE_DMA
if(mUseDma)
{
//使能DMA
mI2C->CR2 |= I2C_CR2_DMAEN;
}
#endif
I2C_InitStructure.I2C_ClockSpeed = mSpeed; //Initialize the I2C_ClockSpeed member
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; // Initialize the I2C_Mode member
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; // Initialize the I2C_DutyCycle member
I2C_InitStructure.I2C_OwnAddress1 = 0; // Initialize the I2C_OwnAddress1 member
I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; // Initialize the I2C_Ack member
I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; // Initialize the I2C_AcknowledgedAddress member
I2C_Init(mI2C,&I2C_InitStructure);//iic初始化
#ifdef I2C_USE_DMA
if(mUseDma)
{
//DMA初始化
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE);
// I2Cx Common Channel Configuration
DMA_InitStructure.DMA_BufferSize = 0;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte ;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
// Select I2Cx DR Address register as DMA PeripheralBaseAddress
DMA_InitStructure.DMA_PeripheralBaseAddr =(uint32_t)&(mI2C->DR);
// Select Memory to Peripheral transfer direction
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_Init(mDmaTxChannel,&DMA_InitStructure);
// Select Peripheral to Memory transfer direction
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_Init(mDmaRxChannel,&DMA_InitStructure);
}
#endif
// Enable the IRQ channel
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
// Configure NVIC for I2Cx EVT Interrupt
NVIC_InitStructure.NVIC_IRQChannel = eventIrq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = mPriority[0];
NVIC_InitStructure.NVIC_IRQChannelSubPriority = mPriority[1];
NVIC_Init(&NVIC_InitStructure);
mI2C->CR2 |= I2C_CR2_ITEVTEN;// 开启I2C事件中断
// Configure NVIC for I2Cx ERR Interrupt
NVIC_InitStructure.NVIC_IRQChannel = errorIrq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = mPriority[2];
NVIC_InitStructure.NVIC_IRQChannelSubPriority = mPriority[3];
NVIC_Init(&NVIC_InitStructure);
mI2C->CR2 |= I2C_CR2_ITERREN;// 开启I2C错误中断
#ifdef I2C_USE_DMA
if(mUseDma)
{
mI2C->CR2 &= ~I2C_IT_BUF; //使用DMA模式时勿打开 BUF中断
}
else//开启了dma开关，但是选择不使用dma功能
{
mI2C->CR2 |= I2C_IT_BUF; //使用中断模式打开BUF中断
}
#else
mI2C->CR2 |= I2C_IT_BUF; //使用中断模式打开BUF中断
#endif
#ifdef I2C_USE_DMA
if(mUseDma)
{
// Configure NVIC for DMA TX channel interrupt
NVIC_InitStructure.NVIC_IRQChannel = dmaTxIrq ;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = mPriority[4];
NVIC_InitStructure.NVIC_IRQChannelSubPriority = mPriority[5];
NVIC_Init(&NVIC_InitStructure);
// Enable DMA TX Channel TCIT
mDmaTxChannel->CCR |= DMA_IT_TC; //打开发送完成中断
// Enable DMA TX Channel TEIT
mDmaTxChannel->CCR |= DMA_IT_TE; //打开错误中断
// Enable DMA TX Channel HTIT
//I2C_DMA_TX_Channel->CCR |= DMA_IT_HT;
// Configure NVIC for DMA RX channel interrupt
NVIC_InitStructure.NVIC_IRQChannel = dmaRxIrq ;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = mPriority[4];
NVIC_InitStructure.NVIC_IRQChannelSubPriority = mPriority[5];
NVIC_Init(&NVIC_InitStructure);
// Enable DMA TX Channel TCIT
mDmaRxChannel->CCR |= DMA_IT_TC; //打开接收完成中断
// Enable DMA TX Channel TEIT
mDmaRxChannel->CCR |= DMA_IT_TE; //打开接收错误中断
// Enable DMA TX Channel HTIT
//I2C_DMA_RX_Channel->CCR |= DMA_IT_HT;
}
#endif
mState=STATE_READY;//队列状态设置为可以开始下一个任务
return 1;
}
