static void icu_unmask_irq(struct irq_data *d)
{
uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
r |= ICU_INT_ROUTE_PJ4_IRQ;
__raw_writel(r, ICU_INT_CONF(d->irq));
}
static void icu_unmask_irq(unsigned int irq)
{
uint32_t r = __raw_readl(ICU_INT_CONF(irq));
r |= ICU_INT_ROUTE_PJ4_IRQ;
__raw_writel(r, ICU_INT_CONF(irq));
}
void __init mmp_wakeupgen_init(void)
{
int irq;
/* disable global irq/fiq in icu for all the cores */
#if defined(CONFIG_CPU_PXA988)
__raw_writel(0x3, PXA988_ICU_CP_GBL_INT_MSK);
__raw_writel(0x3, PXA988_ICU_A9C0_GBL_INT_MSK);
__raw_writel(0x3, PXA988_ICU_A9C1_GBL_INT_MSK);
#elif defined(CONFIG_CPU_PXA1088)
__raw_writel(0x3, PXA1088_ICU_CP_GBL_INT_MSK);
__raw_writel(0x3, PXA1088_ICU_APC0_GBL_INT_MSK);
__raw_writel(0x3, PXA1088_ICU_APC1_GBL_INT_MSK);
__raw_writel(0x3, PXA1088_ICU_APC2_GBL_INT_MSK);
__raw_writel(0x3, PXA1088_ICU_APC3_GBL_INT_MSK);
#endif
/*
* config all the interrupt source be able to interrupt the cpu 0,
* except those which are routed to Seagull
* in IRQ mode, with priority 0 as masked by default.
*/
for (irq = 0; irq < ICU_IRQ_END - ICU_IRQ_START; irq++) {
if (irq == IRQ_PXA988_AIRQ - ICU_IRQ_START
|| irq == IRQ_PXA988_CP_TIMER1 - ICU_IRQ_START
|| irq == IRQ_PXA988_CP_TIMER2_3 - ICU_IRQ_START)
__raw_writel(__raw_readl(ICU_INT_CONF(irq)) &
~ICU_INT_CONF_CPU0, ICU_INT_CONF(irq));
else
__raw_writel(ICU_IRQ_CPU0_MASKED, ICU_INT_CONF(irq));
}
#ifdef CONFIG_CPU_PXA988
if (has_feat_ipc_wakeup_core()) {
/*
* "Trigger IPC interrupt to wake cores when sending IPI"
* Enable the IPC AP3 in ICU to let the IPC interrupt be able to
* wake up two AP cores.
*/
__raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA988_IPC);
__raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA988_IPC);
#define ICU_IRQ_CPU_ALL_ENABLE (ICU_INT_CONF_IRQ_FIQ |\
ICU_INT_CONF_CPU0 | ICU_INT_CONF_CPU1 | ICU_INT_CONF_PRIO(2))
irq = IRQ_PXA988_IPC_AP3 - IRQ_PXA988_START;
__raw_writel(ICU_IRQ_CPU_ALL_ENABLE, ICU_INT_CONF(irq));
}
#endif
gic_arch_extn.irq_mask = icu_mask_irq;
gic_arch_extn.irq_unmask = icu_unmask_irq;
gic_arch_extn.irq_set_affinity = icu_set_affinity;
}
static void pxa168_intc_restore(struct intc_regs *context)
{
unsigned int i;
for (i = 0 ;i < 64;i++)
__raw_writel(context->icu_int_conf[i], ICU_INT_CONF(i));
__raw_writel(context->icu_fiq_sel_int_num, ICU_AP_FIQ_SEL_INT_NUM);
__raw_writel(context->icu_irq_sel_int_num, ICU_AP_IRQ_SEL_INT_NUM);
__raw_writel(context->icu_gbl_irq_msk, ICU_AP_GBL_IRQ_MSK);
__raw_writel(context->icu_dma_int_msk, ICU_DMA_INT_MSK);
__raw_writel(context->icu_dma_int_status, ICU_DMA_INT_STATUS);
__raw_writel(context->icu_int_status_0, ICU_INT_STATUS_0);
__raw_writel(context->icu_int_status_1, ICU_INT_STATUS_1);
__raw_writel(context->icu_ddr_arm_l2_int_msk, ICU_DDR_ARM_L2_INT_MSK);
__raw_writel(context->icu_ddr_arm_l2_int_status, ICU_DDR_ARM_L2_INT_STATUS);
}
static void icu_mask_irq(struct irq_data *d)
{
void __iomem *reg;
unsigned long val;
int irq;
irq = irq_need_handle(d);
if (irq < 0)
return;
reg = ICU_INT_CONF(irq);
val = __raw_readl(reg);
val &= ~0xF;
__raw_writel(val, reg);
}
static void pxa168_intc_save(struct intc_regs *context)
{
unsigned int i;
for (i = 0 ;i < 64;i++)
context->icu_int_conf[i] = __raw_readl(ICU_INT_CONF(i));
context->icu_fiq_sel_int_num = __raw_readl(ICU_AP_FIQ_SEL_INT_NUM);
context->icu_irq_sel_int_num = __raw_readl(ICU_AP_IRQ_SEL_INT_NUM);
context->icu_gbl_irq_msk = __raw_readl(ICU_AP_GBL_IRQ_MSK);
context->icu_dma_int_msk = __raw_readl(ICU_DMA_INT_MSK);
context->icu_dma_int_status = __raw_readl(ICU_DMA_INT_STATUS);
context->icu_int_status_0 = __raw_readl(ICU_INT_STATUS_0);
context->icu_int_status_1 = __raw_readl(ICU_INT_STATUS_1);
context->icu_ddr_arm_l2_int_msk = __raw_readl(ICU_DDR_ARM_L2_INT_MSK);
context->icu_ddr_arm_l2_int_status = __raw_readl(ICU_DDR_ARM_L2_INT_STATUS);
}
static int icu_set_affinity(struct irq_data *d,
const struct cpumask *mask_val, bool force)
{
void __iomem *reg;
unsigned long val;
unsigned int cpu;
int irq;
irq = irq_need_handle(d);
if (irq < 0)
return 0;
cpu = cpumask_first(mask_val);
reg = ICU_INT_CONF(irq);
val = __raw_readl(reg);
val &= ~ICU_INT_CONF_AP_MASK;
val |= ICU_INT_CONF_AP(cpu);
__raw_writel(val, reg);
return 0;
}
static void icu_unmask_irq(struct irq_data *d)
{
__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
}
static void icu_mask_irq(struct irq_data *d)
{
__raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
}
