/**
* Main entry point for the AMD_INIT_POST function.
*
* This entry point is responsible for initializing all system memory,
* gathering important data out of the pre-memory cache storage into a
* temporary holding buffer in main memory. After that APs will be
* shutdown in preparation for the host environment to take control.
* Note: pre-memory stack will be disabled also.
*
* @param[in,out] PostParams Required input parameters for the AMD_INIT_POST
* entry point.
*
* @return Aggregated status across all internal AMD POST calls invoked.
*
*/
AGESA_STATUS
AmdInitPost (
IN OUT AMD_POST_PARAMS *PostParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS AmdInitPostStatus;
WARM_RESET_REQUEST Request;
UINT8 PrevRequestBit;
UINT8 PrevStateBits;
IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITPOST, &PostParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n");
ASSERT (PostParams != NULL);
AmdInitPostStatus = AGESA_SUCCESS;
PrevRequestBit = FALSE;
PrevStateBits = WR_STATE_COLD;
IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
// If a previously requested warm reset cannot be triggered in the
// current stage, store the previous state of request and reset the
// request struct to the current post stage
GetWarmResetFlag (&PostParams->StdHeader, &Request);
if (Request.RequestBit == TRUE) {
if (Request.StateBits >= Request.PostStage) {
PrevRequestBit = Request.RequestBit;
PrevStateBits = Request.StateBits;
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage - 1;
SetWarmResetFlag (&PostParams->StdHeader, &Request);
}
}
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATPOST, &PostParams->StdHeader);
AgesaStatus = GnbInitAtPost (PostParams);
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATPOST, &PostParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_BEGINAMDMEMAUTO, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n");
PostParams->MemConfig.MemData->StdHeader = PostParams->StdHeader;
AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n");
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDAMDMEMAUTO, &PostParams->StdHeader);
if (AgesaStatus != AGESA_FATAL) {
// Check BIST status
AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
//
// P-State data gathered, then, Relinquish APs
//
IDS_PERF_TIMESTAMP (TP_BEGINAMDCPUPOST, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n");
AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n");
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDAMDCPUPOST, &PostParams->StdHeader);
// Warm Reset
GetWarmResetFlag (&PostParams->StdHeader, &Request);
// If a warm reset is requested in the current post stage, trigger the
// warm reset and ignore the previous request
if (Request.RequestBit == TRUE) {
if (Request.StateBits < Request.PostStage) {
AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
}
} else {
// Otherwise, if there's a previous request, restore it
// so that the subsequent post stage can trigger the warm reset
if (PrevRequestBit == TRUE) {
Request.RequestBit = PrevRequestBit;
Request.StateBits = PrevStateBits;
SetWarmResetFlag (&PostParams->StdHeader, &Request);
}
}
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATPOSTAFTERDRAM, &PostParams->StdHeader);
AgesaStatus = GnbInitAtPostAfterDram (PostParams);
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATPOSTAFTERDRAM, &PostParams->StdHeader);
IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n");
//For Heap will be relocate to new address in next stage, flush out debug print buffer if needed
IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader);
// WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here
IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITPOST, &PostParams->StdHeader);
// Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
}
// Check for Cache As Ram Corruption
IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
// At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside
// of AGESA to be recognized by IsWarmReset()
GetWarmResetFlag (&PostParams->StdHeader, &Request);
Request.StateBits = Request.PostStage;
SetWarmResetFlag (&PostParams->StdHeader, &Request);
return AmdInitPostStatus;
}
/**
* Main entry point for the AMD_INIT_RESET function.
*
* This entry point is responsible for establishing the HT links to the program
* ROM and for performing basic processor initialization.
*
* @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET
* entry point.
*
* @return Aggregated status across all internal AMD reset calls invoked.
*
*/
AGESA_STATUS
AmdInitReset (
IN OUT AMD_RESET_PARAMS *ResetParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS CalledAgesaStatus;
WARM_RESET_REQUEST Request;
UINT8 PrevRequestBit;
UINT8 PrevStateBits;
AgesaStatus = AGESA_SUCCESS;
// Setup ROM execution cache
CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]);
if (CalledAgesaStatus > AgesaStatus) {
AgesaStatus = CalledAgesaStatus;
}
// IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader);
// Init Debug Print function
IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString);
AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
ASSERT (ResetParams != NULL);
PrevRequestBit = FALSE;
PrevStateBits = WR_STATE_COLD;
if (IsBsp (&ResetParams->StdHeader, &AgesaStatus)) {
CalledAgesaStatus = BldoptFchFunction.InitReset (ResetParams);
AgesaStatus = (CalledAgesaStatus > AgesaStatus) ? CalledAgesaStatus : AgesaStatus;
}
// If a previously requested warm reset cannot be triggered in the
// current stage, store the previous state of request and reset the
// request struct to the current post stage
GetWarmResetFlag (&ResetParams->StdHeader, &Request);
if (Request.RequestBit == TRUE) {
if (Request.StateBits >= Request.PostStage) {
PrevRequestBit = Request.RequestBit;
PrevStateBits = Request.StateBits;
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage - 1;
SetWarmResetFlag (&ResetParams->StdHeader, &Request);
}
}
// Initialize the PCI MMIO access mechanism
InitializePciMmio (&ResetParams->StdHeader);
// Initialize Hyper Transport Registers
if (HtOptionInitReset.HtInitReset != NULL) {
IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n");
CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig);
IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n");
if (CalledAgesaStatus > AgesaStatus) {
AgesaStatus = CalledAgesaStatus;
}
}
// Warm Reset, should be at the end of AmdInitReset
GetWarmResetFlag (&ResetParams->StdHeader, &Request);
// If a warm reset is requested in the current post stage, trigger the
// warm reset and ignore the previous request
if (Request.RequestBit == TRUE) {
if (Request.StateBits < Request.PostStage) {
AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader);
}
} else {
// Otherwise, if there's a previous request, restore it
// so that the subsequent post stage can trigger the warm reset
if (PrevRequestBit == TRUE) {
Request.RequestBit = PrevRequestBit;
Request.StateBits = PrevStateBits;
SetWarmResetFlag (&ResetParams->StdHeader, &Request);
}
}
// Check for Cache As Ram Corruption
IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n");
AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader);
return AgesaStatus;
}
/**
* Perform initialization services required at the Early Init POST time point.
*
* Execution Cache, HyperTransport, and AP Init advanced services are performed.
*
* @param[in] EarlyParams The interface struct for all early services
*
* @return The most severe AGESA_STATUS returned by any called service.
*
*/
AGESA_STATUS
AmdInitEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParams
)
{
AGESA_STATUS CalledAgesaStatus;
AGESA_STATUS EarlyInitStatus;
WARM_RESET_REQUEST Request;
AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);
IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
ASSERT (EarlyParams != NULL);
EarlyInitStatus = AGESA_SUCCESS;
GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
Request.RequestBit = FALSE;
SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader);
// Setup ROM execution cache
CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
if (CalledAgesaStatus > EarlyInitStatus) {
EarlyInitStatus = CalledAgesaStatus;
}
// Full Hypertransport Initialization
// IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs.
CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig);
if (CalledAgesaStatus > EarlyInitStatus) {
EarlyInitStatus = CalledAgesaStatus;
}
// AP launch
CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig);
if (CalledAgesaStatus > EarlyInitStatus) {
EarlyInitStatus = CalledAgesaStatus;
}
// Warm Rest, should be at the end of AmdInitEarly
GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
if (Request.RequestBit == TRUE) {
Request.RequestBit = FALSE;
Request.StateBits = WR_STATE_EARLY;
SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader);
} else {
if (Request.StateBits < WR_STATE_EARLY) {
Request.StateBits = WR_STATE_EARLY;
SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
}
}
CalledAgesaStatus = GnbInitAtEarly (
&EarlyParams->StdHeader,
&EarlyParams->PlatformConfig,
&EarlyParams->GnbConfig
);
if (CalledAgesaStatus > EarlyInitStatus) {
EarlyInitStatus = CalledAgesaStatus;
}
// Check for Cache As Ram Corruption
IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader);
IDS_OPTION_HOOK (IDS_AFTER_WARM_RESET, EarlyParams, &EarlyParams->StdHeader);
IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader);
IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader);
return EarlyInitStatus;
}
