/*
* i82596 Support Routines for MVME1[67][27] and MVME187 Boards
*/
static void
ie_reset(struct ie_softc *sc, int why)
{
struct ie_pcctwo_softc *ps;
u_int32_t scp_addr;
ps = (struct ie_pcctwo_softc *) sc;
switch (why) {
case CHIP_PROBE:
case CARD_RESET:
bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_UPPER,
IE_PORT_RESET);
bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_LOWER, 0);
delay(1000);
/*
* Set the BUSY and BUS_USE bytes here, since the MI code
* incorrectly assumes it can use byte addressing to set it.
* (due to wrong-endianess of the chip)
*/
ie_write_16(sc, IE_ISCP_BUSY(sc->iscp), 1);
ie_write_16(sc, IE_SCP_BUS_USE(sc->scp), IE_BUS_USE);
scp_addr = sc->scp + (u_int) sc->sc_iobase;
scp_addr |= IE_PORT_ALT_SCP;
bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_UPPER,
scp_addr & 0xffff);
bus_space_write_2(ps->ps_bust, ps->ps_bush, IE_MPUREG_LOWER,
(scp_addr >> 16) & 0xffff);
delay(1000);
break;
}
}
/* Reset the adapter. */
void
ie_gsc_reset(struct ie_softc *sc, int what)
{
struct ie_gsc_softc *gsc = (struct ie_gsc_softc *) sc;
int i;
switch (what) {
case CHIP_PROBE:
bus_space_write_4(gsc->iot, gsc->ioh, IE_GSC_REG_RESET, 0);
break;
case CARD_RESET:
bus_space_write_4(gsc->iot, gsc->ioh, IE_GSC_REG_RESET, 0);
/*
* per [2] 4.6.2.1
* delay for 10 system clocks + 5 transmit clocks,
* NB: works for system clocks over 10MHz
*/
DELAY(1000);
/*
* after the hardware reset:
* inform i825[89]6 about new SCP address,
* which must be at least 16-byte aligned
*/
ie_gsc_port(sc, IE_PORT_ALT_SCP);
ie_gsc_attend(sc, what);
for (i = 9000; i-- && ie_gsc_read16(sc, IE_ISCP_BUSY(sc->iscp));
DELAY(100))
pdcache(0, (vaddr_t)sc->sc_maddr + sc->iscp, IE_ISCP_SZ);
#if I82596_DEBUG
if (i < 0) {
printf("timeout for PORT command (%x)%s\n",
ie_gsc_read16(sc, IE_ISCP_BUSY(sc->iscp)),
(gsc->flags & IEGSC_GECKO)? " on gecko":"");
return;
}
#endif
break;
}
}
