void UART1_Write( const uint8_t byte) { INT_DISABLE(); *uart1_obj.txTail = byte; uart1_obj.txTail++; if (uart1_obj.txTail == (uart1_txByteQ + UART1_CONFIG_TX_BYTEQ_LENGTH)) { uart1_obj.txTail = uart1_txByteQ; } uart1_obj.txStatus.s.empty = false; if (uart1_obj.txHead == uart1_obj.txTail) { uart1_obj.txStatus.s.full = true; } INT_ENABLE(); if (IEC0bits.U1TXIE == false) { IEC0bits.U1TXIE = true ; } }
/******************************************************************************* * ow_write_byte *******************************************************************************/ void ow_write_byte(const _Gpio_Descriptor *Gpio, u8 Val) { u8 i; INT_DISABLE(); for (i = 0 ; i < 8 ; i++) ow_write_bit(Gpio, (Val >> i) & 0x01); INT_ENABLE(); }
static int __s3c4510b_stop(struct net_device *dev) { // Disable irqs INT_DISABLE(INT_BDMARX); INT_DISABLE(INT_MACTX); outl( 0, REG_BDMATXCON); outl( 0, REG_BDMARXCON); outl( 0, REG_MACTXCON); outl( 0, REG_MACRXCON); free_irq(INT_BDMARX, dev); free_irq(INT_MACTX, dev); netif_stop_queue(dev); return 0; }
/******************************************************************************* * ow_read_byte *******************************************************************************/ u8 ow_read_byte(const _Gpio_Descriptor *Gpio) { u8 i; u8 val = 0; INT_DISABLE(); for (i = 0 ; i < 8 ; i++) if (ow_read_bit(Gpio)) val |= 1 << i; INT_ENABLE(); return(val); }
/******************************************************************************* * ow_reset *******************************************************************************/ u8 ow_reset(const _Gpio_Descriptor *Gpio) { u8 val; INT_DISABLE(); DQ_LO(Gpio); OW_DELAY_480(); DQ_HI(Gpio); OW_DELAY_70(); val = !DQ_VAL(Gpio); OW_DELAY_410(); INT_ENABLE(); return(val); //1 = Dectected / 0 = Not detected }
int main(int argc, char **argv) { char *kernel = NULL; char *ptr, *mem, *rdptr; void (*func)(); int fd, size, c; int i; progname = argv[0]; /* getopt... */ for (i = 1; i < argc; i++) { if (argv[i][0] != '-') { if (kernel == NULL) { kernel = argv[i]; } } else if (argv[i][0] == '-') { if (argv[i][1] == '0') { turbo_mode = !turbo_mode; } else { usage(); } } } if (kernel == NULL) kernel = "/mmc0/netbsd.bin"; printf("\r\nNetBSD boot loader ver." NBBOOT_VERSION "\r\n"); rdptr = 0; ptr = malloc(0x2000); if (ptr == 0) { printf("No memory\r\n"); return -1; } memset(ptr, 0, 0x2000); fd = open(kernel, OptRead); if (fd == -1) { free(ptr); printf("can't open %s\r\n", kernel); return -1; } switch(MCR) { case 0x5224: strcpy(ptr + 0x1100, "mem=8M console=ttySC1,115200 root=/dev/shmmc2"); break; case 0x522c: strcpy(ptr + 0x1100, "mem=16M console=ttySC1,115200 root=/dev/shmmc2"); break; case 0x526c: strcpy(ptr + 0x1100, "mem=32M console=ttySC1,115200 root=/dev/shmmc2"); break; case 0x5274: strcpy(ptr + 0x1100, "mem=64M console=ttySC1,115200 root=/dev/shmmc2"); break; default: printf("SDRAM not found!!\r\n"); return -1; } mem = (char *)KERNEL_TEXTADDR; func = (void *)KERNEL_TEXTADDR; printf("NetBSD kernel loading."); c = 0; do { size = read(fd, mem, 0x4000); mem = &mem[0x4000]; if((++c & 0x7) == 0) putchar('.'); } while (size == 0x4000); putchar('\r'), putchar('\n'); close(fd); if (turbo_mode) hw_config(HW_CONFIG_TURBO, 1, 0); sleep(500); INT_DISABLE(); WTCSR_WR = 0xa500; memcpy((char *)0x8c000000, ptr, 0x2000); (*func)(); /*NOTREACHED*/ return 0; }
/*! * \brief Initialize system timer. * * This function is automatically called by Nut/OS * during system initialization. * * Nut/OS uses on-chip timer 0 for its timer services. * Applications should not modify any registers of this * timer, but make use of the Nut/OS timer API. Timer 1 * and timer 2 are available to applications. */ void NutRegisterTimer(void (*handler) (void *)) { os_handler = handler; #if defined(MCU_AT91R40008) /* Disable the Clock Counter */ outr(TC0_CCR, TC_CLKDIS); /* Disable all interrupts */ outr(TC0_IDR, 0xFFFFFFFF); /* Clear the status register. */ dummy = inr(TC0_SR); /* Select divider and compare trigger */ outr(TC0_CMR, TC_CLKS_MCK32 | TC_CPCTRG); /* Enable the Clock counter */ outr(TC0_CCR, TC_CLKEN); /* Validate the RC compare interrupt */ outr(TC0_IER, TC_CPCS); /* Disable timer 0 interrupts. */ outr(AIC_IDCR, _BV(TC0_ID)); /* Set the TC0 IRQ handler address */ outr(AIC_SVR(4), (unsigned int)Timer0Entry); /* Set the trigg and priority for timer 0 interrupt */ /* Level 7 is highest, level 0 lowest. */ outr(AIC_SMR(4), (AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4)); /* Clear timer 0 interrupt */ outr(AIC_ICCR, _BV(TC0_ID)); /* Enable timer 0 interrupts */ outr(AIC_IECR, _BV(TC0_ID)); /* Set compare value for 1 ms. */ outr(TC0_RC, 0x80F); /* Software trigger starts the clock. */ outr(TC0_CCR, TC_SWTRG); #elif defined(MCU_S3C4510B) INT_DISABLE(IRQ_TIMER); CSR_WRITE(TCNT0, 0); CSR_WRITE(TDATA0, CLOCK_TICK_RATE); CSR_WRITE(TMOD, TMOD_TIMER0_VAL); CLEAR_PEND_INT(IRQ_TIMER); NutRegisterIrqHandler( &InterruptHandlers[IRQ_TIMER], handler, 0); INT_ENABLE(IRQ_TIMER); #elif defined(MCU_GBA) /* Disable master interrupt. */ outw(REG_IME, 0); /* Set global interrupt vector. */ NutRegisterIrqHandler(&sig_TMR3, Timer3Entry, 0); /* Enable timer and timer interrupts. */ outdw(REG_TMR3CNT, TMR_IRQ_ENA | TMR_ENA | 48756); /* Enable timer 3 interrupts. */ outw(REG_IE, inw(REG_IE) | INT_TMR3); /* Enable master interrupt. */ outw(REG_IME, 1); #else #warning "MCU not defined" #endif }
static int __s3c4510b_open(struct net_device *dev) { unsigned long status; /* Disable interrupts */ INT_DISABLE(INT_BDMARX); INT_DISABLE(INT_MACTX); /** ** install RX ISR **/ __rx_irqaction.dev_id = (void *)dev; status = setup_irq( INT_BDMARX, &__rx_irqaction); if ( unlikely(status)) { printk( KERN_ERR "Unabled to hook irq %d for ethernet RX\n", INT_BDMARX); return status; } /** ** install TX ISR **/ __tx_irqaction.dev_id = (void *)dev; status = setup_irq( INT_MACTX, &__tx_irqaction); if ( unlikely(status)) { printk( KERN_ERR "Unabled to hook irq %d for ethernet TX\n", INT_MACTX); return status; } /* setup DBMA and MAC */ outl( ETH_BRxRS, REG_BDMARXCON); /* reset BDMA RX machine */ outl( ETH_BTxRS, REG_BDMATXCON); /* reset BDMA TX machine */ outl( ETH_SwReset, REG_MACCON); /* reset MAC machine */ outl( sizeof( ETHFrame), REG_BDMARXLSZ); outl( ETH_FullDup, REG_MACCON); /* enable full duplex */ /* init frame descriptors */ TxFDinit( dev); RxFDinit( dev); outl( (dev->dev_addr[0] << 24) | (dev->dev_addr[1] << 16) | (dev->dev_addr[2] << 8) | (dev->dev_addr[3]) , REG_CAM_BASE); outl( (dev->dev_addr[4] << 24) | (dev->dev_addr[5] << 16) , REG_CAM_BASE + 4); outl( 0x0001, REG_CAMEN); outl( ETH_CompEn | /* enable compare mode (check against the CAM) */ ETH_BroadAcc, /* accept broadcast packetes */ REG_CAMCON); INT_ENABLE(INT_BDMARX); INT_ENABLE(INT_MACTX); /* enable RX machinery */ outl( ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */ ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */ ETH_BRxMAINC | /* BDMA Rx Memory Address increment */ ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */ ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */ ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */ ETH_BRxLittle | /* BDMA Rx Little endian */ ETH_BRxWA10 | /* BDMA Rx Word Alignment- two invalid bytes */ ETH_BRxEn, /* BDMA Rx Enable */ REG_BDMARXCON); outl( ETH_RxEn | /* enable MAC RX */ ETH_StripCRC | /* check and strip CRC */ ETH_EnCRCErr | /* interrupt on CRC error */ ETH_EnOver | /* interrupt on overflow error */ ETH_EnLongErr | /* interrupt on long frame error */ ETH_EnRxPar, /* interrupt on MAC FIFO parity error */ REG_MACRXCON); netif_start_queue(dev); return 0; }
void s3c4510b_mask_ack_irq(unsigned int irq) { INT_DISABLE(irq); }
static void __s3c4510b_ack_irq(unsigned int irq) { /* Acknowledge, clear _AND_ disable the interrupt. */ INT_DISABLE( irq); CLEAR_PEND_INT( irq); }
static void __s3c4510b_mask_irq(unsigned int irq) { INT_DISABLE( irq); }