/*
* Clock-Architecture Diagram 4
*/
COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
RK1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK1108_CLKGATE_CON(6), 0, GFLAGS),
GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED,
RK1108_CLKGATE_CON(17), 0, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
RK1108_CLKSEL_CON(29), 0, 5, DFLAGS,
RK1108_CLKGATE_CON(7), 2, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
RK1108_CLKSEL_CON(29), 8, 5, DFLAGS,
RK1108_CLKGATE_CON(7), 3, GFLAGS),
INVERTER(0, "pclk_vip", "ext_vip",
RK1108_CLKSEL_CON(31), 8, IFLAGS),
GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
RK1108_CLKGATE_CON(7), 6, GFLAGS),
GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
RK1108_CLKGATE_CON(18), 10, GFLAGS),
GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
RK1108_CLKGATE_CON(6), 5, GFLAGS),
GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
RK1108_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0,
RK1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS),
/*
* Clock-Architecture Diagram 5
*/
RK3288_CLKSEL_CON(21), 4, 1, MFLAGS), GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0, RK3288_CLKGATE_CON(5), 3, GFLAGS), GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0, RK3288_CLKGATE_CON(5), 2, GFLAGS), GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0, RK3288_CLKGATE_CON(5), 0, GFLAGS), GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0, RK3288_CLKGATE_CON(5), 1, GFLAGS), COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, RK3288_CLKGATE_CON(2), 6, GFLAGS), MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0, RK3288_CLKSEL_CON(22), 4, 1, MFLAGS), INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", RK3288_CLKSEL_CON(22), 7, IFLAGS), GATE(0, "jtag", "ext_jtag", 0, RK3288_CLKGATE_CON(4), 14, GFLAGS), COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0, RK3288_CLKSEL_CON(13), 11, 2, MFLAGS, RK3288_CLKGATE_CON(5), 14, GFLAGS), COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, RK3288_CLKGATE_CON(3), 6, GFLAGS), GATE(0, "hsicphy12m_xin12m", "xin12m", 0, RK3288_CLKGATE_CON(13), 9, GFLAGS), DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0, RK3288_CLKSEL_CON(11), 8, 6, DFLAGS), MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
RK3368_CLKGATE_CON(4), 4, GFLAGS), COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0, RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3368_CLKGATE_CON(4), 1, GFLAGS), GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0, RK3368_CLKGATE_CON(4), 2, GFLAGS), COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0, RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS, RK3368_CLKGATE_CON(4), 9, GFLAGS), GATE(0, "pclk_isp_in", "ext_isp", 0, RK3368_CLKGATE_CON(17), 2, GFLAGS), INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in", RK3368_CLKSEL_CON(21), 6, IFLAGS), GATE(0, "pclk_vip_in", "ext_vip", 0, RK3368_CLKGATE_CON(16), 13, GFLAGS), INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in", RK3368_CLKSEL_CON(21), 13, IFLAGS), GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, RK3368_CLKGATE_CON(4), 13, GFLAGS), GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, RK3368_CLKGATE_CON(4), 12, GFLAGS), COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(21), 15, 1, MFLAGS, RK3368_CLKGATE_CON(4), 5, GFLAGS), COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
RK2928_CLKGATE_CON(2), 2, GFLAGS), COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, RK2928_CLKGATE_CON(2), 3, GFLAGS), MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, RK2928_CLKGATE_CON(3), 7, GFLAGS), MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0, RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), GATE(0, "pclkin_cif0", "ext_cif0", 0, RK2928_CLKGATE_CON(3), 3, GFLAGS), INVERTER(0, "pclk_cif0", "pclkin_cif0", RK2928_CLKSEL_CON(30), 8, IFLAGS), FACTOR(0, "xin12m", "xin24m", 0, 1, 2), /* * the 480m are generated inside the usb block from these clocks, * but they are also a source for the hsicphy clock. */ GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 5, GFLAGS), GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 6, GFLAGS), COMPOSITE(0, "mac_src", mux_mac_p, 0, RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 5, GFLAGS),
