ide_startstop_t redwood_ide_intr (ide_drive_t *drive)
{
int i;
byte dma_stat;
unsigned int nsect;
ide_hwgroup_t *hwgroup = HWGROUP(drive);
struct request *rq = hwgroup->rq;
unsigned long block,b1,b2,b3,b4;
nsect = rq->current_nr_sectors;
dma_stat = HWIF(drive)->dmaproc(ide_dma_end, drive);
rq->sector += nsect;
rq->buffer += nsect<<9;
rq->errors = 0;
i = (rq->nr_sectors -= nsect);
ide_end_request(1, HWGROUP(drive));
if (i > 0) {
b1 = IN_BYTE(IDE_SECTOR_REG);
b2 = IN_BYTE(IDE_LCYL_REG);
b3 = IN_BYTE(IDE_HCYL_REG);
b4 = IN_BYTE(IDE_SELECT_REG);
block = ((b4 & 0x0f) << 24) + (b3 << 16) + (b2 << 8) + (b1);
block++;
if (drive->select.b.lba) {
OUT_BYTE(block,IDE_SECTOR_REG);
OUT_BYTE(block>>=8,IDE_LCYL_REG);
OUT_BYTE(block>>=8,IDE_HCYL_REG);
OUT_BYTE(((block>>8)&0x0f)|drive->select.all,IDE_SELECT_REG);
} else {
/*
* promise_read_intr() is the handler for disk read/multread interrupts
*/
static ide_startstop_t promise_read_intr (ide_drive_t *drive)
{
byte stat;
int i;
unsigned int sectors_left, sectors_avail, nsect;
struct request *rq;
if (!OK_STAT(stat=GET_STAT(),DATA_READY,BAD_R_STAT)) {
return ide_error(drive, "promise_read_intr", stat);
}
read_again:
do {
sectors_left = IN_BYTE(IDE_NSECTOR_REG);
IN_BYTE(IDE_SECTOR_REG);
} while (IN_BYTE(IDE_NSECTOR_REG) != sectors_left);
rq = HWGROUP(drive)->rq;
sectors_avail = rq->nr_sectors - sectors_left;
read_next:
rq = HWGROUP(drive)->rq;
if ((nsect = rq->current_nr_sectors) > sectors_avail)
nsect = sectors_avail;
sectors_avail -= nsect;
ide_input_data(drive, rq->buffer, nsect * SECTOR_WORDS);
#ifdef DEBUG
printk("%s: promise_read: sectors(%ld-%ld), buffer=0x%08lx, "
"remaining=%ld\n", drive->name, rq->sector, rq->sector+nsect-1,
(unsigned long) rq->buffer+(nsect<<9), rq->nr_sectors-nsect);
#endif
rq->sector += nsect;
rq->buffer += nsect<<9;
rq->errors = 0;
i = (rq->nr_sectors -= nsect);
if ((rq->current_nr_sectors -= nsect) <= 0)
ide_end_request(1, HWGROUP(drive));
if (i > 0) {
if (sectors_avail)
goto read_next;
stat = GET_STAT();
if(stat & DRQ_STAT)
goto read_again;
if(stat & BUSY_STAT) {
ide_set_handler (drive, &promise_read_intr, WAIT_CMD, NULL);
return ide_started;
}
printk("Ah! promise read intr: sectors left !DRQ !BUSY\n");
return ide_error(drive, "promise read intr", stat);
}
return ide_stopped;
}
/*
* pdc4030_cmd handles the set of vendor specific commands that are initiated
* by command F0. They all have the same success/failure notification.
*/
int pdc4030_cmd(ide_drive_t *drive, byte cmd)
{
unsigned long timeout, timer;
byte status_val;
promise_selectproc(drive); /* redundant? */
OUT_BYTE(0xF3,IDE_SECTOR_REG);
OUT_BYTE(cmd,IDE_SELECT_REG);
OUT_BYTE(PROMISE_EXTENDED_COMMAND,IDE_COMMAND_REG);
timeout = HZ * 10;
timeout += jiffies;
do {
if(time_after(jiffies, timeout)) {
return 2; /* device timed out */
}
/* This is out of delay_10ms() */
/* Delays at least 10ms to give interface a chance */
timer = jiffies + (HZ + 99)/100 + 1;
while (time_after(timer, jiffies));
status_val = IN_BYTE(IDE_SECTOR_REG);
} while (status_val != 0x50 && status_val != 0x70);
if(status_val == 0x50)
return 0; /* device returned success */
else
return 1; /* device returned failure */
}
static int
pmac_ide_do_setfeature(ide_drive_t *drive, byte command)
{
unsigned long flags;
byte old_select;
int result = 1;
save_flags(flags);
cli();
old_select = IN_BYTE(IDE_SELECT_REG);
OUT_BYTE(drive->select.all, IDE_SELECT_REG);
udelay(10);
OUT_BYTE(IDE_SETXFER, IDE_FEATURE_REG);
OUT_BYTE(command, IDE_NSECTOR_REG);
if(wait_for_ready(drive)) {
printk("pmac_ide_do_setfeature disk not ready before SET_FEATURE!\n");
goto out;
}
OUT_BYTE(IDE_SETFEATURE, IDE_COMMAND_REG);
result = wait_for_ready(drive);
if (result)
printk("pmac_ide_do_setfeature disk not ready after SET_FEATURE !\n");
out:
OUT_BYTE(old_select, IDE_SELECT_REG);
restore_flags(flags);
return result;
}
static void ps2_ide_select(ide_drive_t *drive)
{
int retry;
unsigned long timeout;
ide_hwif_t *hwif = HWIF(drive);
if (drive->drive_data || drive->select.b.unit)
return;
DPRINT("waiting for spinup... 0x%x", hwif->io_ports[0]);
for (retry = 0; retry < 160; retry++) { /* 50msec X 160 = 8sec */
/* write select command */
OUT_BYTE(drive->select.all, hwif->io_ports[IDE_SELECT_OFFSET]);
/* wait 50msec */
timeout = jiffies + ((HZ + 19)/20) + 1;
while (0 < (signed long)(timeout - jiffies));
/* see if we've select successfully */
if (IN_BYTE(hwif->io_ports[IDE_SELECT_OFFSET]) ==
drive->select.all) {
DPRINTK(": OK");
break;
}
}
DPRINTK("\n");
drive->drive_data = 1;
}
/*
* Update the
*/
int ide_driveid_update (ide_drive_t *drive)
{
/*
* Re-read drive->id for possible DMA mode
* change (copied from ide-probe.c)
*/
struct hd_driveid *id;
unsigned long timeout, flags;
SELECT_MASK(HWIF(drive), drive, 1);
if (IDE_CONTROL_REG)
OUT_BYTE(drive->ctl,IDE_CONTROL_REG);
ide_delay_50ms();
OUT_BYTE(WIN_IDENTIFY, IDE_COMMAND_REG);
timeout = jiffies + WAIT_WORSTCASE;
do
{
if (0 < (signed long)(jiffies - timeout))
{
SELECT_MASK(HWIF(drive), drive, 0);
return 0; /* drive timed-out */
}
ide_delay_50ms(); /* give drive a breather */
}
while (IN_BYTE(IDE_ALTSTATUS_REG) & BUSY_STAT);
ide_delay_50ms(); /* wait for IRQ and DRQ_STAT */
if (!OK_STAT(GET_STAT(),DRQ_STAT,BAD_R_STAT))
{
SELECT_MASK(HWIF(drive), drive, 0);
printk("%s: CHECK for good STATUS\n", drive->name);
return 0;
}
__save_flags(flags); /* local CPU only */
__cli(); /* local CPU only; some systems need this */
SELECT_MASK(HWIF(drive), drive, 0);
id = kmalloc(SECTOR_WORDS*4, GFP_ATOMIC);
if (!id)
{
__restore_flags(flags); /* local CPU only */
return 0;
}
ide_input_data(drive, id, SECTOR_WORDS);
(void) GET_STAT(); /* clear drive IRQ */
ide__sti(); /* local CPU only */
__restore_flags(flags); /* local CPU only */
ide_fix_driveid(id);
if (id)
{
drive->id->dma_ultra = id->dma_ultra;
drive->id->dma_mword = id->dma_mword;
drive->id->dma_1word = id->dma_1word;
/* anything more ? */
kfree(id);
}
return 1;
}
static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
{
struct hd_driveid *id = drive->id;
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
unsigned long high_16 = pci_resource_start(dev, 4);
unsigned long dma_base = hwif->dma_base;
byte unit = (drive->select.b.unit & 0x01);
unsigned int drive_conf;
byte drive_pci;
byte test1, test2, speed = -1;
byte AP;
unsigned short EP;
byte CLKSPD = IN_BYTE(high_16 + 0x11);
byte udma_33 = ultra ? (inb(high_16 + 0x001f) & 1) : 0;
byte udma_66 = ((eighty_ninty_three(drive)) && udma_33) ? 1 : 0;
byte udma_100 = (((dev->device == PCI_DEVICE_ID_PROMISE_20265) || (dev->device == PCI_DEVICE_ID_PROMISE_20267)) && udma_66) ? 1 : 0;
/*
* Set the control register to use the 66Mhz system
* clock for UDMA 3/4 mode operation. If one drive on
* a channel is U66 capable but the other isn't we
* fall back to U33 mode. The BIOS INT 13 hooks turn
* the clock on then off for each read/write issued. I don't
* do that here because it would require modifying the
* kernel, seperating the fop routines from the kernel or
* somehow hooking the fops calls. It may also be possible to
* leave the 66Mhz clock on and readjust the timing
* parameters.
*/
byte mask = hwif->channel ? 0x08 : 0x02;
unsigned short c_mask = hwif->channel ? (1<<11) : (1<<10);
byte ultra_66 = ((id->dma_ultra & 0x0010) ||
(id->dma_ultra & 0x0008)) ? 1 : 0;
byte ultra_100 = ((id->dma_ultra & 0x0020) ||
(id->dma_ultra & 0x0010) ||
(id->dma_ultra & 0x0008)) ? 1 : 0;
pci_read_config_word(dev, 0x50, &EP);
if (((ultra_66) || (ultra_100)) && (EP & c_mask)) {
#ifdef DEBUG
printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->channel ? "Secondary", "Primary");
printk(" Switching to Ultra33 mode.\n");
#endif /* DEBUG */
/* Primary : zero out second bit */
/* Secondary : zero out fourth bit */
OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
} else {
/*
* do_pdc4030_io() is called from do_rw_disk, having had the block number
* already set up. It issues a READ or WRITE command to the Promise
* controller, assuming LBA has been used to set up the block number.
*/
ide_startstop_t do_pdc4030_io (ide_drive_t *drive, struct request *rq)
{
unsigned long timeout;
byte stat;
if (rq->cmd == READ) {
ide_set_handler(drive, &promise_read_intr, WAIT_CMD, NULL);
OUT_BYTE(PROMISE_READ, IDE_COMMAND_REG);
/* The card's behaviour is odd at this point. If the data is
available, DRQ will be true, and no interrupt will be
generated by the card. If this is the case, we need to simulate
an interrupt. Ugh! Otherwise, if an interrupt will occur, bit0
of the SELECT register will be high, so we can just return and
be interrupted.*/
timeout = jiffies + HZ/20; /* 50ms wait */
do {
stat=GET_STAT();
if(stat & DRQ_STAT) {
disable_irq(HWIF(drive)->irq);
ide_intr(HWIF(drive)->irq,HWGROUP(drive),NULL);
enable_irq(HWIF(drive)->irq);
return ide_stopped;
}
if(IN_BYTE(IDE_SELECT_REG) & 0x01)
return ide_started;
udelay(1);
} while (time_before(jiffies, timeout));
printk("%s: reading: No DRQ and not waiting - Odd!\n",
drive->name);
return ide_started;
}
if (rq->cmd == WRITE) {
ide_startstop_t startstop;
OUT_BYTE(PROMISE_WRITE, IDE_COMMAND_REG);
if (ide_wait_stat(&startstop, drive, DATA_READY, drive->bad_wstat, WAIT_DRQ)) {
printk("%s: no DRQ after issuing PROMISE_WRITE\n", drive->name);
return startstop;
}
if (!drive->unmask)
__cli(); /* local CPU only */
HWGROUP(drive)->wrq = *rq; /* scratchpad */
return promise_write(drive);
}
printk("%s: bad command: %d\n", drive->name, rq->cmd);
ide_end_request(0, HWGROUP(drive));
return ide_stopped;
}
/* Calculate PIO timings */
static void
pmac_ide_tuneproc(ide_drive_t *drive, byte pio)
{
ide_pio_data_t d;
int i;
u32 *timings;
int accessTicks, recTicks;
i = pmac_ide_find(drive);
if (i < 0)
return;
pio = ide_get_best_pio_mode(drive, pio, 4, &d);
accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
if (drive->select.all & 0x10)
timings = &pmac_ide[i].timings[1];
else
timings = &pmac_ide[i].timings[0];
if (pmac_ide[i].kind == controller_kl_ata4) {
/* The "ata-4" IDE controller of Core99 machines */
accessTicks = SYSCLK_TICKS_UDMA(ide_pio_timings[pio].active_time * 1000);
recTicks = SYSCLK_TICKS_UDMA(d.cycle_time * 1000) - accessTicks;
*timings = ((*timings) & 0x1FFFFFC00) | accessTicks | (recTicks << 5);
} else {
/* The old "ata-3" IDE controller */
accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
if (accessTicks < 4)
accessTicks = 4;
recTicks = SYSCLK_TICKS(d.cycle_time) - accessTicks - 4;
if (recTicks < 1)
recTicks = 1;
*timings = ((*timings) & 0xFFFFFF800) | accessTicks | (recTicks << 5);
}
#ifdef IDE_PMAC_DEBUG
printk(KERN_ERR "ide_pmac: Set PIO timing for mode %d, reg: 0x%08x\n",
pio, *timings);
#endif
if (drive->select.all == IN_BYTE(IDE_SELECT_REG))
pmac_ide_selectproc(drive);
}
static int
pmac_ide_dma_onoff(ide_drive_t *drive, int enable)
{
int ata4, udma, idx;
struct hd_driveid *id = drive->id;
drive->using_dma = 0;
idx = pmac_ide_find(drive);
if (idx < 0)
return 0;
if (drive->media == ide_floppy)
enable = 0;
if (((id->capability & 1) == 0) && !check_drive_lists(drive, GOOD_DMA_DRIVE))
enable = 0;
if (check_drive_lists(drive, BAD_DMA_DRIVE))
enable = 0;
udma = 0;
ata4 = (pmac_ide[idx].kind == controller_kl_ata4);
if(enable) {
if (ata4 && (drive->media == ide_disk) &&
(id->field_valid & 0x0004) && (id->dma_ultra & 0x17)) {
/* UltraDMA modes. */
drive->using_dma = pmac_ide_udma_enable(drive, idx);
}
if (!drive->using_dma && (id->dma_mword & 0x0007)) {
/* Normal MultiWord DMA modes. */
drive->using_dma = pmac_ide_mdma_enable(drive, idx);
}
/* Without this, strange things will happen on Keylargo-based
* machines
*/
OUT_BYTE(0, IDE_CONTROL_REG);
if (drive->select.all == IN_BYTE(IDE_SELECT_REG))
pmac_ide_selectproc(drive);
}
return 0;
}
/*
* promise_write_pollfunc() is the handler for disk write completion polling.
*/
static ide_startstop_t promise_write_pollfunc (ide_drive_t *drive)
{
int i;
ide_hwgroup_t *hwgroup = HWGROUP(drive);
struct request *rq;
if (IN_BYTE(IDE_NSECTOR_REG) != 0) {
if (time_before(jiffies, hwgroup->poll_timeout)) {
ide_set_handler (drive, &promise_write_pollfunc, 1, NULL);
return ide_started; /* continue polling... */
}
printk("%s: write timed-out!\n",drive->name);
return ide_error (drive, "write timeout", GET_STAT());
}
if (ide_multwrite(drive, 4))
return ide_stopped;
rq = hwgroup->rq;
for (i = rq->nr_sectors; i > 0;) {
i -= rq->current_nr_sectors;
ide_end_request(1, hwgroup);
}
return ide_stopped;
}
/*
init_pdc4030: Test for presence of a Promise caching controller card.
Returns: 0 if no Promise card present at this io_base
1 if Promise card found
*/
int init_pdc4030 (void)
{
ide_startstop_t startstop;
ide_hwif_t *hwif = hwif_required;
ide_drive_t *drive;
ide_hwif_t *second_hwif;
struct dc_ident ident;
int i;
if (!hwif) return 0;
drive = &hwif->drives[0];
second_hwif = &ide_hwifs[hwif->index+1];
if(hwif->chipset == ide_pdc4030) /* we've already been found ! */
return 1;
if(IN_BYTE(IDE_NSECTOR_REG) == 0xFF || IN_BYTE(IDE_SECTOR_REG) == 0xFF)
{
return 0;
}
OUT_BYTE(0x08,IDE_CONTROL_REG);
if(pdc4030_cmd(drive,PROMISE_GET_CONFIG)) {
return 0;
}
if(ide_wait_stat(&startstop,drive,DATA_READY,BAD_W_STAT,WAIT_DRQ)) {
printk("%s: Failed Promise read config!\n",hwif->name);
return 0;
}
ide_input_data(drive,&ident,SECTOR_WORDS);
if(ident.id[1] != 'P' || ident.id[0] != 'T') {
return 0;
}
printk("%s: Promise caching controller, ",hwif->name);
switch(ident.type) {
case 0x43: printk("DC4030VL-2, "); break;
case 0x41: printk("DC4030VL-1, "); break;
case 0x40: printk("DC4030VL, "); break;
default: printk("unknown - type 0x%02x - please report!\n"
,ident.type);
return 0;
}
printk("%dKB cache, ",(int)ident.cache_mem);
switch(ident.irq) {
case 0x00: hwif->irq = 14; break;
case 0x01: hwif->irq = 12; break;
default: hwif->irq = 15; break;
}
printk("on IRQ %d\n",hwif->irq);
hwif->chipset = second_hwif->chipset = ide_pdc4030;
hwif->mate = second_hwif;
second_hwif->mate = hwif;
second_hwif->channel = 1;
hwif->selectproc = second_hwif->selectproc = &promise_selectproc;
/* Shift the remaining interfaces down by one */
for (i=MAX_HWIFS-1 ; i > hwif->index+1 ; i--) {
ide_hwif_t *h = &ide_hwifs[i];
printk("Shifting i/f %d values to i/f %d\n",i-1,i);
ide_init_hwif_ports(h->io_ports, (h-1)->io_ports[IDE_DATA_OFFSET], NULL);
h->io_ports[IDE_CONTROL_OFFSET] = (h-1)->io_ports[IDE_CONTROL_OFFSET];
h->noprobe = (h-1)->noprobe;
}
ide_init_hwif_ports(second_hwif->io_ports, hwif->io_ports[IDE_DATA_OFFSET], NULL);
second_hwif->io_ports[IDE_CONTROL_OFFSET] = hwif->io_ports[IDE_CONTROL_OFFSET];
second_hwif->irq = hwif->irq;
for (i=0; i<2 ; i++) {
hwif->drives[i].io_32bit = 3;
second_hwif->drives[i].io_32bit = 3;
if(!ident.current_tm[i+2].cyl) second_hwif->drives[i].noprobe=1;
}
return 1;
}
