void alt_up_pixel_buffer_clear_screen(alt_up_pixel_buffer_dev *pixel_buffer, int backbuffer)
/* This function clears the screen by setting each pixel to a black color. */
{
register unsigned int addr;
register unsigned int limit_x, limit_y;
/* Set up the address to start clearing from and the screen boundaries. */
if (backbuffer == 1)
addr = pixel_buffer->back_buffer_start_address;
else
addr = pixel_buffer->buffer_start_address;
limit_x = pixel_buffer->x_resolution;
/* In 16 and 32-bit color modes we use twice or four times more memory for the display buffer.*/
if (pixel_buffer->color_mode == ALT_UP_16BIT_COLOR_MODE) {
limit_x = limit_x << 1;
} else {
limit_x = limit_x << 2;
}
limit_y = pixel_buffer->y_resolution;
if (pixel_buffer->addressing_mode == ALT_UP_PIXEL_BUFFER_XY_ADDRESS_MODE) {
/* Clear the screen when the VGA is set up in an XY addressing mode. */
register unsigned int x,y;
register unsigned int offset_y;
offset_y = pixel_buffer->y_coord_offset;
for (y = 0; y < limit_y; y++)
{
for (x = 0; x < limit_x; x = x + 4)
{
IOWR_32DIRECT(addr, x, 0);
}
addr = addr + (1 << offset_y);
}
} else {
/* Clear the screen when the VGA is set up in a linear addressing mode. */
register int x;
limit_y = limit_x*limit_y;
for (x = 0; x < limit_y; x = x + 4)
{
IOWR_32DIRECT(addr, x, 0);
}
}
}
void sd_card_start_read_sector(int index)
{
/* Multiply sector offset by sector size to get the address. Sector size is 512. Also,
* the SD card reads data in 512 byte chunks, so the address must be a multiple of 512. */
IOWR_32DIRECT(command_argument_register, 0, (sectors[index] + fat_partition_offset_in_512_byte_sectors)*512);
IOWR_16DIRECT(command_register, 0, CMD_READ_BLOCK);
current_sector_index = sectors[index]+fat_partition_offset_in_512_byte_sectors;
}
static void txrxDoneCache0(void * handle, void * data)
{
txrx_doneCache0 = 1;
if(load_q_cache0 == 1)
IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000001);
else
load_q_cache0 = 1;
}
int alt_up_pixel_buffer_swap_buffers(alt_up_pixel_buffer_dev *pixel_buffer)
/* This function swaps the front and back buffers. At the next refresh cycle the back buffer will be drawn on the screen
* and will become the front buffer. */
{
register unsigned int temp = pixel_buffer->back_buffer_start_address;
IOWR_32DIRECT(pixel_buffer->base, 0, 1);
pixel_buffer->back_buffer_start_address = pixel_buffer->buffer_start_address;
pixel_buffer->buffer_start_address = temp;
return 0;
}
/******************************************************************
* Function: MemTestDevice
*
* Purpose: Tests that every bit in the memory device within the
* specified address range can store both a '1' and a '0'.
*
******************************************************************/
static int MemTestDevice(unsigned int memory_base, unsigned int nBytes)
{
unsigned int offset;
unsigned int pattern;
unsigned int antipattern;
unsigned int ret_code = 0x0;
/* Fill memory with a known pattern. */
for (pattern = 1, offset = 0; offset < nBytes; pattern++, offset+=4)
{
IOWR_32DIRECT(memory_base, offset, pattern);
}
printf(" .");
/* Check each location and invert it for the second pass. */
for (pattern = 1, offset = 0; offset < nBytes; pattern++, offset+=4)
{
if (IORD_32DIRECT(memory_base, offset) != pattern)
{
ret_code = (memory_base + offset);
break;
}
antipattern = ~pattern;
IOWR_32DIRECT(memory_base, offset, antipattern);
}
printf(" .");
/* Check each location for the inverted pattern and zero it. */
for (pattern = 1, offset = 0; offset < nBytes; pattern++, offset+=4)
{
antipattern = ~pattern;
if (IORD_32DIRECT(memory_base, offset) != antipattern)
{
ret_code = (memory_base + offset);
break;
}
IOWR_32DIRECT(memory_base, offset, 0x0);
}
return ret_code;
}
void helper_plot_pixel(register unsigned int buffer_start, register int line_size, register int x, register int y, register int color, register int mode)
/* This is a helper function that draws a pixel at a given location. Note that no boundary checks are made,
* so drawing off-screen may cause unpredictable side effects. */
{
if (mode == 0)
IOWR_8DIRECT(buffer_start, line_size*y+x, color);
else if (mode == 1)
IOWR_16DIRECT(buffer_start, (line_size*y+x) << 1, color);
else
IOWR_32DIRECT(buffer_start, (line_size*y+x) << 2, color);
}
static void interruptServiceRoutine()
{
int readdata;
int update_gfstart = 0;
// Reset SOFISTS and EOFISTS
readdata = IORD_32DIRECT(REGFILE_FINAL_0_BASE, GINT);
SET_BIT(readdata, 1);
SET_BIT(readdata, 3);
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, GINT, readdata);
// Set SHHT and Grab controls
readdata = IORD_32DIRECT(REGFILE_FINAL_0_BASE, GCTRL);
if (CHECK_BIT(readdata, 5))
{
CLEAR_BIT(readdata, 5);
update_gfstart = 1;
}
else
{
SET_BIT(readdata, 5);
}
// Set the SHHT
SET_BIT(readdata, 0);
// Write the control register
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, GCTRL, readdata);
// Update GFSTART to new line location
readdata = IORD_32DIRECT(REGFILE_FINAL_0_BASE, GFSTART);
if (update_gfstart == 1)
{
readdata += GFSTART_increment - 1;
}
else
{
readdata += 1;
}
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, GFSTART, readdata);
}
/*
* Get system console GUI soft button state from debug memory
*/
void debug_get_buttons(int offset, int num_buttons, int *buttons)
{
int i;
int val;
unsigned int base_address = IO_IN_BUTTONS_BASE + offset;
*buttons = 0;
for (i=0;i<num_buttons;i++) {
val = IORD_32DIRECT(base_address,i*4);
*buttons = *buttons | ((val != 0) << i);
IOWR_32DIRECT(base_address, i*4, 0); //reset button value
}
}
int main()
{
alt_up_pixel_buffer_dma_dev* pixel_buffer;
pixel_buffer = alt_up_pixel_buffer_dma_open_dev("/dev/video_pixel_buffer_dma_0");
if (pixel_buffer == 0) {
printf("error initializing pixel buffer (check name in alt_up_pixel_buffer_dma_open_dev)\n");
}
alt_up_pixel_buffer_dma_change_back_buffer_address(pixel_buffer, PIXEL_BUFFER_BASE);
alt_up_pixel_buffer_dma_swap_buffers(pixel_buffer);
while (alt_up_pixel_buffer_dma_check_swap_buffers_status(pixel_buffer));
alt_up_pixel_buffer_dma_clear_screen(pixel_buffer, 0);
int hw = 0;
if (hw) {
IOWR_32DIRECT(drawer_base,0,10); // Set x1
IOWR_32DIRECT(drawer_base,4,20); // Set y1
IOWR_32DIRECT(drawer_base,8,50); // Set x2
IOWR_32DIRECT(drawer_base,12,60); // Set y2
IOWR_32DIRECT(drawer_base,16,0xFFFF); // Set colour
IOWR_32DIRECT(drawer_base,20,1); // Start drawing
while(IORD_32DIRECT(drawer_base,20)==0); // wait until done
} else {
alt_up_pixel_buffer_dma_draw_box(pixel_buffer, 10,20,50,60,0xFFFF,0);
}
return 0;
}
void generate_p3(unsigned char size_x, unsigned char size_y, unsigned char max_color)
{
unsigned char* shared;
unsigned char bar_color[8][3] = {
{255, 255, 255}, // White
{255, 255, 0 }, // Yellow
{0 , 255, 255}, // Cyan
{0 , 255, 0 }, // Green
{255, 0 , 255}, // Magenta
{255, 0 , 0 }, // Red
{0, 0 , 255}, // Blue
{0, 0 , 0}, // Black
};
int x, y;
shared = (unsigned char*) SHARED_ONCHIP_BASE;
printf("Waiting for %d\n", shared);
while(IORD_32DIRECT(shared, 0) != 0) {}
//delay
shared++;
IOWR_32DIRECT(shared++, 0, size_y);
IOWR_32DIRECT(shared++, 0, max_color);
for (y = 0; y < size_y; y++){
for (x = 0; x < size_x; x++){
unsigned char color;
color = y / (size_y / 8);
IOWR_32DIRECT(shared++, 0, bar_color[color][0]);
IOWR_32DIRECT(shared++, 0, bar_color[color][1]);
IOWR_32DIRECT(shared++, 0, bar_color[color][2]);
}
}
IOWR_32DIRECT(SHARED_ONCHIP_BASE, 0, size_x);
}
int main()
{
int readdata = 0;
int offset = 0;
int toggle = 0;
int data = 0xDEAD;
// Register IRQ
alt_irq_register(0, 0, interruptServiceRoutine);
// Enable DMA
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, DMACTRL, 0x1);
// Set DMA start address to 0
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, DMAFSTART, 0);
// Write DMA line pitch
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, DMALPITCH, LINE_PITCH);
// Set Grab start address to 0
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, GFSTART, 0);
// Enable a snapshot and write 10 to GMODE // MUST BE STARTED AT 10
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, GCTRL, 0x51);
// Write the line pitch
IOWR_32DIRECT(REGFILE_FINAL_0_BASE, GLPITCH, LINE_PITCH);
while (1)
{
}
return 0;
}
void HandleClassSpecificControlRequests(volatile __CONTROL_REQUEST_STATUS *PCtrlReqStatus,
volatile unsigned int base, char stage)
{
if(PCtrlReqStatus->PUsbCtrlReq->bmRequestType.RequestType == 0x01)
{
//if Class specific request is there
//printf("Class Req\n");
if( (PCtrlReqStatus->PUsbCtrlReq->bRequest == 0xFE) &&
(PCtrlReqStatus->PUsbCtrlReq->bmRequestType.Direction == 1) &&
(PCtrlReqStatus->PUsbCtrlReq->bmRequestType.RequestType == 1) &&
(PCtrlReqStatus->PUsbCtrlReq->wIndex.Value == 0) &&
(PCtrlReqStatus->PUsbCtrlReq->wValue.Value == 0) &&
(PCtrlReqStatus->PUsbCtrlReq->wLength == 1) )
{
//printf("GetMaxLUN\n");
PCtrlReqStatus->sizeOfDataStageData = 1;
PCtrlReqStatus->PDataStageData = &DataToBeSent;
}
else if( (PCtrlReqStatus->PUsbCtrlReq->bRequest == 0xFF) &&
(PCtrlReqStatus->PUsbCtrlReq->bmRequestType.Direction == 0) &&
(PCtrlReqStatus->PUsbCtrlReq->bmRequestType.RequestType == 1) &&
(PCtrlReqStatus->PUsbCtrlReq->wIndex.Value == 0) &&
(PCtrlReqStatus->PUsbCtrlReq->wValue.Value == 0) &&
(PCtrlReqStatus->PUsbCtrlReq->wLength == 0))
{
int csr = IORD_32DIRECT(base, 0x50);
IOWR_32DIRECT(base, 0x50, csr | 0x00800000);
csr = IORD_32DIRECT(base, 0x60);
IOWR_32DIRECT(base, 0x60, csr | 0x00800000);
}
else
{
// printf("Bad control request\n");
int csr = IORD_32DIRECT(base, 0x40);
IOWR_32DIRECT(base, 0x40, csr | 0x00800000);
}
}
}
void draw_line(int x1, int y1, int x2, int y2, unsigned char color)
{
IOWR_32DIRECT(CI_DRAW_LINE_0_BASE, 0, SDRAM_0_BASE + SDRAM_VIDEO_OFFSET); // Frame address
IOWR_32DIRECT(CI_DRAW_LINE_0_BASE, 4, x1); // X1
IOWR_32DIRECT(CI_DRAW_LINE_0_BASE, 8, y1); // Y1
IOWR_32DIRECT(CI_DRAW_LINE_0_BASE, 12, x2); // X2
IOWR_32DIRECT(CI_DRAW_LINE_0_BASE, 16, y2); // Y2
IOWR_32DIRECT(CI_DRAW_LINE_0_BASE, 20, color); // Color
ALT_CI_CI_DRAW_LINE_0;
}
int main(int i, char ** pp, char ** ppp)
{
int REG_ADDR;
volatile int readData;
// Read address 0
REG_ADDR = 0;
int counter = 0;
while (1)
{
readData = IORD_32DIRECT(REG_0_BASE, REG_ADDR);
IOWR_32DIRECT(REG_0_BASE, REG_ADDR + 8, counter + readData);
counter++;
}
return 0;
}
/**
* Wprowadzenie klucza do modulu deszyfrujacego Triple DES
*/
void init_3desdecrypt (unsigned int key11,unsigned int key12,unsigned int key21,unsigned int key22,unsigned int key31,unsigned int key32)
{
IOWR_32DIRECT (A_3DESDECRYPT_0_BASE,0x00000000,key11); //wprowadzenie pierwszej polowy klucza 1
IOWR_32DIRECT (A_3DESDECRYPT_0_BASE,0x00000004,key12);//wprowadzenie drugiej polowy klucza 1
IOWR_32DIRECT (A_3DESDECRYPT_0_BASE,0x00000008,key21); //wprowadzenie pierwszej polowy klucza 2
IOWR_32DIRECT(A_3DESDECRYPT_0_BASE,0x0000000C,key22); //wprowadzenie drugiej polowy klucza 2
IOWR_32DIRECT ( A_3DESDECRYPT_0_BASE,0x00000010,key31);//wprowadzenie pierwszej polowy klucza 3
IOWR_32DIRECT(A_3DESDECRYPT_0_BASE,0x000000014,key32); //wprowadzenie drugiej polowy klucza 3
}
/******************************************************************
* Function: MemTestDataBus
*
* Purpose: Tests that the data bus is connected with no
* stuck-at's, shorts, or open circuits.
*
******************************************************************/
static int MemTestDataBus(unsigned int address)
{
unsigned int pattern;
unsigned int ret_code = 0x0;
/* Perform a walking 1's test at the given address. */
for (pattern = 1; pattern != 0; pattern <<= 1)
{
/* Write the test pattern. */
IOWR_32DIRECT(address, 0, pattern);
/* Read it back (immediately is okay for this test). */
if (IORD_32DIRECT(address, 0) != pattern)
{
ret_code = pattern;
break;
}
}
return ret_code;
}
//------------------------------------------------------------------------------
void openmac_timerSetCompareValue(UINT timer_p, UINT32 val_p)
{
UINT offset;
switch (timer_p)
{
case HWTIMER_SYNC:
offset = OPENMAC_TIMER_OFFSET_CMP_VAL;
break;
case HWTIMER_EXT_SYNC:
offset = OPENMAC_TIMER_OFFSET_2ND_CMP_VAL;
break;
default:
return;
}
IOWR_32DIRECT(OPENMAC_TIMER_BASE, offset, val_p);
}
//------------------------------------------------------------------------------
void openmac_timerIrqDisable(UINT timer_p)
{
UINT offset;
switch (timer_p)
{
case HWTIMER_SYNC:
offset = OPENMAC_TIMER_OFFSET_CTRL;
break;
case HWTIMER_EXT_SYNC:
offset = OPENMAC_TIMER_OFFSET_2ND_CTRL;
break;
default:
return;
}
IOWR_32DIRECT(OPENMAC_TIMER_BASE, offset, 0);
}
void draw(int x1, int y1, int x2, int y2, int colour) {
IOWR_32DIRECT(drawer_base, 0, x1);
// Set x1
IOWR_32DIRECT(drawer_base, 4, y1);
// Set y1
IOWR_32DIRECT(drawer_base, 8, x2);
// Set x2
IOWR_32DIRECT(drawer_base, 12, y2);
// Set y2
IOWR_32DIRECT(drawer_base, 16, colour);
// Set colour
IOWR_32DIRECT(drawer_base, 20, 1);
// Start drawing
while (IORD_32DIRECT(drawer_base,20) == 0)
; // wait until done
}
//------------------------------------------------------------------------------
void openmac_timerIrqEnable(UINT timer_p, UINT32 pulseWidthNs_p)
{
UINT offset;
UINT32 value;
switch (timer_p)
{
case HWTIMER_SYNC:
offset = OPENMAC_TIMER_OFFSET_CTRL;
value = 1;
break;
case HWTIMER_EXT_SYNC:
offset = OPENMAC_TIMER_OFFSET_2ND_CTRL;
value = 1 | (OMETH_NS_2_TICKS(pulseWidthNs_p) << 1);
break;
default:
return;
}
IOWR_32DIRECT(OPENMAC_TIMER_BASE, offset, value);
}
/**
* Wprowadzenie klucza do modulu deszyfrujacego Triple DES potokowego
*/
void init_3des_decrypt_pot (unsigned int key11,unsigned int key12,unsigned int key21,unsigned int key22,unsigned int key31,unsigned int key32)
{
IOWR_32DIRECT (A_3DESDECRYPT_POT_0_BASE,0x00000000,key11); //wprowadzenie pierwszej polowy klucza 1
//unsigned int iserted_key11 = IORD_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x0000001C);
IOWR_32DIRECT (A_3DESDECRYPT_POT_0_BASE,0x00000004,key12); //wprowadzenie drugiej polowy klucza 1
//unsigned int iserted_key12 = IORD_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x00000020);
//printf("Klucz pierwszy: 0x%x%x \n",iserted_key11,iserted_key12);
IOWR_32DIRECT (A_3DESDECRYPT_POT_0_BASE,0x00000008,key21);//wprowadzenie pierwszej polowy klucza 2
//unsigned int iserted_key21 = IORD_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x00000024);
IOWR_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x0000000C,key22); //wprowadzenie drugiej polowy klucza 2
//unsigned int iserted_key22 = IORD_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x00000028);
//printf("Klucz drugi: 0x%x%x \n",iserted_key21,iserted_key22);
IOWR_32DIRECT ( A_3DESDECRYPT_POT_0_BASE,0x00000010,key31);//wprowadzenie pierwszej polowy klucza 3
//unsigned int iserted_key31 = IORD_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x0000002C);
IOWR_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x000000014,key32); //wprowadzenie drugiej polowy klucza 3
//unsigned int iserted_key32 = IORD_32DIRECT(A_3DESDECRYPT_POT_0_BASE,0x00000030);
//printf("Klucz trzeci: 0x%x%x \n",iserted_key31,iserted_key32);
}
static void demo_mandelbrot(void)
{
static const float args[][6] = {
{-2.4f, -1.2f, 1.28f, 0.64f, 0.0f, 0.0f},
{-0.843333f, -0.111628f, 0.042667f, 0.021333f, 0.0f, 0.0f},
{-0.775333f, -0.111628f, 0.0042667f, 0.0021333f, 0.0f, 0.0f},
};
lcd_write(0x50, 0);
lcd_write(0x51, LCD_WIDTH-1);
lcd_write(0x52, 0);
lcd_write(0x53, LCD_HEIGHT-1);
lcd_write(0x03, 0x1028);
int i = 0;
do
{
lcd_write(0x21, 0);
lcd_write(0x20, 0);
lcd_write_address(0x22);
alt_u32 *params = (alt_u32*)args[i];
IOWR_32DIRECT(MB_FLOAT_BASE, 0*4, params[0]);
IOWR_32DIRECT(MB_FLOAT_BASE, 1*4, params[1]);
IOWR_32DIRECT(MB_FLOAT_BASE, 2*4, params[2]);
IOWR_32DIRECT(MB_FLOAT_BASE, 3*4, params[3]);
IOWR_32DIRECT(MB_FLOAT_BASE, 4*4, params[4]);
IOWR_32DIRECT(MB_FLOAT_BASE, 5*4, params[5]);
IOWR_32DIRECT(MB_FLOAT_BASE, 7*4, 0x0);
while(IORD_32DIRECT(MB_FLOAT_BASE, 7*4) & 1);
mdelay(2000);
if(++i >= (sizeof(args) / sizeof(*args))) i = 0;
}
while(DEMO_MODE() == DEMO_MANDELBROT);
lcd_write(0x03, LCD_ENTRYMODE);
}
int main(void)
{
int enable = 1;
int XLENGTH = 55; // xlength = 55
int XDIAG_DEMI = 30; // xdiag_demi = 30
int YDIAG_DEMI = 55; // ydiag_demi = 32
int XYDIAG_DEMI = (XDIAG_DEMI << 10) | YDIAG_DEMI;
int RANK1_X_OFFSET = 600;
int RANK1_Y_OFFSET = 100;
int RANK1_XY_OFFSET = (RANK1_X_OFFSET << 10) | RANK1_Y_OFFSET;
// int QBERT_POSITION_X0 = RANK1_X_OFFSET - 2*XLENGTH - 2*XDIAG_DEMI - 1; // x0 = 600
int QBERT_POSITION_X0 = RANK1_X_OFFSET; // x0 = 600
int QBERT_POSITION_Y0 = RANK1_Y_OFFSET + 2*YDIAG_DEMI; // yo = 90
int QBERT_POSITION_XY0 = (QBERT_POSITION_X0 << 10) | QBERT_POSITION_Y0;
// int QBERT_POSITION_X1 = RANK1_X_OFFSET - 1;
// int QBERT_POSITION_Y1 = RANK1_Y_OFFSET + 4*YDIAG_DEMI;
// int QBERT_POSITION_XY1 = (QBERT_POSITION_X1 << 10) | QBERT_POSITION_Y1;
int qbert_jump = 2;
IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE,0, enable);
IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE,4, XLENGTH);
IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE,8, XYDIAG_DEMI);
IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE,12, RANK1_XY_OFFSET);
IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE,16, QBERT_POSITION_XY0);
// IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE,20, QBERT_POSITION_XY1);
IOWR_32DIRECT(NIOS_MTL_CONTROLLER_0_BASE, 24, qbert_jump);
printf("Move my Qbert!\n");
/*
while(1){
IOWR_32DIRECT(QBERT_MOVE_0_BASE,0, XLENGTH);
IOWR_32DIRECT(QBERT_MOVE_0_BASE,4, XDIAG_DEMI | (YDIAG_DEMI << 11));
IOWR_32DIRECT(QBERT_MOVE_0_BASE,8, X0 | (Y0 << 11));
length_m = IORD_32DIRECT(QBERT_MOVE_0_BASE,0);
XYDIAG_m = IORD_32DIRECT(QBERT_MOVE_0_BASE,4);
XY_m = IORD_32DIRECT(QBERT_MOVE_0_BASE,8);
printf("length :'%d' and diag : '%d' and xy : '%d'\n",length_m, XYDIAG_m,XY_m);
// IOWR_32DIRECT(QBERT_MOVE_0_BASE,12, enable);
// IOWR_32DIRECT(QBERT_MOVE_0_BASE,16, enable);
}*/
return 0;
}
//
// Low level write function for Biss interface
//
void Biss_Write(unsigned int base_addr, unsigned int reg, unsigned int data) {
IOWR_32DIRECT(base_addr, reg, data);
}
/**
* alt_epcq_controller_write_block
*
* This function writes one block/sector of data to flash. The length of the write can NOT
* spill into the adjacent sector.
*
* It assumes that someone has already erased the appropriate sector(s).
*
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
* - block_offset: byte-addressed offset, from the start of flash, of the sector to written to
* - data-offset: Byte offset (unaligned access) of write into flash memory.
* For best performance, word(32 bits - aligned access) offset of write is recommended.
* - *src_addr: source buffer
* - length: size of writing
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -EIO -> write failed, sector might be protected
**/
int alt_epcq_controller_write_block
(
alt_flash_dev *flash_info, /** flash device info */
int block_offset, /** sector/block offset in byte addressing */
int data_offset, /** offset of write from base address */
const void *data, /** data to be written */
int length /** bytes of data to be written, >0 */
)
{
alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */
alt_u32 remaining_length = length; /** length left to write */
alt_u32 write_offset = data_offset; /** offset into flash to write too */
alt_epcq_controller_dev *epcq_flash_info = (alt_epcq_controller_dev*)flash_info;
/*
* Sanity checks that data offset is not larger then a sector, that block offset is
* sector aligned and within the valid flash memory range and a write doesn't spill into
* the adjacent flash sector.
*/
if(block_offset < 0
|| data_offset < 0
|| NULL == flash_info
|| NULL == data
|| data_offset >= epcq_flash_info->size_in_bytes
|| block_offset >= epcq_flash_info->size_in_bytes
|| length > (epcq_flash_info->sector_size - (data_offset - block_offset))
|| length < 0
|| (block_offset & (epcq_flash_info->sector_size - 1)) != 0)
{
return -EINVAL;
}
/*
* Do writes one 32-bit word at a time.
* We need to make sure that we pad the first few bytes so they're word aligned if they are
* not already.
*/
while (remaining_length > 0)
{
alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */
alt_u32 padding = 0; /** bytes to pad the next word that is written */
alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */
/*
* we need to make sure the write is word aligned
* this should only be true at most 1 time
*/
if (0 != (write_offset & (sizeof(alt_u32) - 1)))
{
/*
* data is not word aligned
* calculate padding bytes need to add before start of a data offset
*/
padding = write_offset & (sizeof(alt_u32) - 1);
/* update variables to account for padding being added */
bytes_to_copy -= padding;
if(bytes_to_copy > remaining_length)
{
bytes_to_copy = remaining_length;
}
write_offset = write_offset - padding;
if(0 != (write_offset & (sizeof(alt_u32) - 1)))
{
return -EINVAL;
}
}
else
{
if(bytes_to_copy > remaining_length)
{
bytes_to_copy = remaining_length;
}
}
/* prepare the word to be written */
memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy);
/* update offset and length variables */
buffer_offset += bytes_to_copy;
remaining_length -= bytes_to_copy;
/* write to flash 32 bits at a time */
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);
/* check whether write triggered a illegal write interrupt */
if((IORD_ALTERA_EPCQ_CONTROLLER_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK) ==
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE)
{
/* clear register */
IOWR_ALTERA_EPCQ_CONTROLLER_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK );
return -EIO; /** write failed, sector might be protected */
}
/* update current offset */
write_offset = write_offset + sizeof(alt_u32);
}
return 0;
}
INT main( )
{
const DWORD N_COL_SCREEN = VGA_RESOLUTION_WIDTH / N_VGA_PIXEL_PER_ONCE;
DWORD i = 0;
DWORD j = 0;
volatile DWORD * p_color_line = NULL;
PRINTS( "The VGA driver started\n" );
#ifdef VGA_EMUL
puts( "VGA emul mode\n" );
const int DUMP_FRAME = 3;
// initialize the driver
if( vga_emul_init( ) == FALSE )
{
PRINTS( "FILE OPEN ERROR!\n" );
}
#endif
while( !vga_is_refreshing( ) );
puts( "vga initial refresh\n" );
DEADPLL( N_VGA_CLK_V_SYNC );
while( TRUE )
{
// process superfield
// process vsync
IOWR_32DIRECT( IO_ADDR_VGA, 0, VGA_COLOR_V_SYNC );
IOWR_8DIRECT( IO_ADDR_VGA, 1, VGA_CONTROL_V_SYNC_ON );
DEADPLL( N_VGA_CLK_V_BP );
IOWR_8DIRECT( IO_ADDR_VGA, 1, VGA_CONTROL_V_SYNC_OFF );
PRINTS( "VSYNC PROCESSED\n" );
// process back-porch line
// during back-porch line, refresh the screen buffer
if( vga_is_refreshing( ) )
{
vga_toggle_graphic_buffer( );
puts( "vga refreshed\n" );
#ifdef VGA_EMUL
n_frame++;
// puts( "n_frame: %d\n", n_frame );
if( n_frame == DUMP_FRAME )
{
puts( "start dump\n" );
}
#endif
}
DEADPLL( N_VGA_CLK_H_SYNC );
PRINTS( "BP LINE PROCESSED\n" );
// draw field
for( i = 0; i < VGA_RESOLUTION_HEIGHT; i++ )
{
// process hsync
IOWR_32DIRECT( IO_ADDR_VGA, 0, VGA_COLOR_H_SYNC );
IOWR_8DIRECT( IO_ADDR_VGA, 1, VGA_CONTROL_H_SYNC_ON );
//p_color_line = &_screen[ _current_buffer ][ i ][ 0 ]; // access the screen memory in advance
p_color_line = ( _screen + ( *( _current_buffer ) * VGA_RESOLUTION_HEIGHT * N_COL_SCREEN ) + ( i * N_COL_SCREEN ) ); // access the screen memory in advance
j = N_COL_SCREEN - 1;
DEADPLL( N_VGA_CLK_H_BP );
IOWR_8DIRECT( IO_ADDR_VGA, 1, VGA_CONTROL_H_SYNC_OFF );
PRINTS( "HSYNC PROCESSED\n" );
int tmp = *p_color_line;
int limit = ( int ) ( p_color_line + N_COL_SCREEN - 1 );
// process back-porch pixel
PRINTS( "BP PIXEL PROCESSED\n" );
// draw horizontal pixels
do
{
#ifdef VGA_EMUL
if( n_frame == DUMP_FRAME )
{
vga_emul_plot_pixel( *p_color_line );
}
#else
DEADPLLI( "10" );
IOWR_32DIRECT( IO_ADDR_VGA, 0, *p_color_line );
#endif
} while( ( int ) p_color_line++ < ( int ) limit );
// process front-porch pixel
DEADPLL( N_VGA_CLK_H_FP );
IOWR_32DIRECT( IO_ADDR_VGA, 0, VGA_COLOR_H_FP );
DEADPLL( N_VGA_CLK_H_SYNC );
PRINTS( "FP PIXEL PROCESSED\n" );
}
//puts( "FRAME DRAWING END: %d\n", i );
#ifdef VGA_EMUL
if( n_frame == DUMP_FRAME )
{
puts( "end dump\n" );
}
#endif
// process front-porch line
IOWR_32DIRECT( IO_ADDR_VGA, 0, VGA_COLOR_V_FP );
DEADPLL( N_VGA_CLK_V_FP - N_VGA_CLK_H_SYNC );
DEADPLL( N_VGA_CLK_V_SYNC );
PRINTS( "FP LINE PROCESSED\n" );
}
return 0;
}
void tclrpt_initialize (debug_data_t *debug_data_ptr)
{
alt_u32 i;
/* Set the pointers to the memory used to communicate
* with the TCL scripts.
*/
if (debug_data_ptr == 0)
{
// If the debug data pointer is NULL then initialize to disallow any access
// Set the register file offset for the data to be 0
#if !HPS_HW
IOWR_32DIRECT (REG_FILE_DEBUG_DATA_ADDR, 0, 0);
#endif
// Initialize all pointers to NULL
debug_summary_report = 0;
debug_cal_report = 0;
debug_margin_report = 0;
debug_printf_output = 0;
debug_data = 0;
}
else
{
// Set the register file offset for the data
#if !HPS_HW
IOWR_32DIRECT (REG_FILE_DEBUG_DATA_ADDR, 0, (alt_u32)debug_data_ptr);
#endif
// Set the global pointers
debug_data = debug_data_ptr;
debug_summary_report = &(debug_data->summary_report);
debug_cal_report = &(debug_data->cal_report);
debug_margin_report = &(debug_data->margin_report);
#if ENABLE_PRINTF_LOG
debug_printf_output = &(debug_data->printf_output);
#else
debug_printf_output = 0;
#endif
debug_emif_toolkit_debug_data = &(debug_data->emif_toolkit_debug_data);
// Initialize the status
debug_data->status = 0;
// Update local pointers
debug_data->summary_report_ptr = (alt_u32)debug_summary_report;
debug_data->cal_report_ptr = (alt_u32)debug_cal_report;
debug_data->margin_report_ptr = (alt_u32)debug_margin_report;
#if ENABLE_DQSEN_SWEEP
debug_data->di_report_ptr = (alt_u32)(&debug_data->di_report);
#endif
debug_data->emif_toolkit_debug_data_ptr = (alt_u32)(&debug_data->emif_toolkit_debug_data);
// Set the sizes of the structs
debug_data->data_size = sizeof(debug_data_t);
debug_summary_report->data_size = sizeof(debug_summary_report_t);
debug_cal_report->data_size = sizeof(debug_cal_report_t);
debug_margin_report->data_size = sizeof(debug_margin_report_t);
#if ENABLE_DQSEN_SWEEP
debug_data->di_report.data_size = sizeof(rw_manager_di_report_t);
debug_data->di_report.max_samples = NUM_DI_SAMPLE;
#endif
debug_emif_toolkit_debug_data->data_size = sizeof(emif_toolkit_debug_data_t);
// Set the initial value of the report flags
debug_summary_report->report_flags = 0;
debug_cal_report->report_flags = 0;
debug_margin_report->report_flags = 0;
#if ENABLE_DQSEN_SWEEP
debug_data->di_report.flags = 0;
#endif
// Initialize the command status
debug_data->command_status = TCLDBG_TX_STATUS_CMD_EXE;
debug_data->requested_command = TCLDBG_CMD_NOP;
for (i = 0; i < COMMAND_PARAM_WORDS; i++)
{
debug_data->command_parameters[i] = 0;
}
#if ENABLE_PRINTF_LOG
// Initialize the size and pointers
debug_data->printf_output_ptr = (alt_u32)debug_printf_output;
debug_printf_output->data_size = sizeof(debug_printf_output_t);
// Initialize the payload
tclrpt_initialize_printf_output();
#else
debug_data->printf_output_ptr = (alt_u32)0;
#endif
}
}
int main()
{
int class; //da trasformate in alt_u8 o 16 in base alle dimensioni
int vote;
int end_class;
alt_u16 command[256];
alt_u16 ack_cmd[3];
alt_u32 tr_size;
alt_u32 tr_size_count;
alt_u8 q_size;
alt_u32 n_packet;
alt_u32 tr_val;
alt_u64 addr; //verificare dimensione
alt_u64 q_addr;
alt_u32 q_val;
alt_u32 i = 0;
alt_u32 k = 0;
alt_u8 k_val;
alt_u16 n_dim;
alt_u16 n_load;
alt_u16 n_load_count;
alt_u16 n_cell;
alt_u16 n_cell_last;
alt_u64 count = 0;
alt_u16 cache_q_addr = 0;
alt_dma_txchan txchan;
alt_dma_rxchan rxchan;
alt_u32 memptr = 0;
alt_u8 empty0 = 0;
alt_u8 empty1 = 0;
alt_u8 overflow = 0;
unsigned char ledvalue = 1;
void* tx_data; /* pointer to data to send */
void* rx_buffer; /* pointer to rx buffer */
while(1)
{
command[0] = 0;
recv_short(command, 8);
//send back the ACK
ack_cmd[0] = ACK;
ack_cmd[1] = ACK;
ack_cmd[2] = command[3];
send_short(ack_cmd, 3);
if(command[0] == FLUSH_COMM)
{
tr_size = 0;
tr_size = command[1];
tr_size = tr_size<<16;
tr_size = tr_size | command[2];
n_packet = 0;
n_packet = command[3];
n_packet = n_packet<<16;
n_packet = n_packet | command[4];
cache_q_addr = command[5];
addr = 0;
tr_size_count = 0;
for(i = 0; i < n_packet;i++)
{
recv_short(command, 256);
send_short(command, 256);
for(k = 0;k < 127; k++)
{
if(tr_size_count < tr_size)
{
tr_size_count = tr_size_count + 1;
tr_val = 0;
tr_val = command[2+2*k];
tr_val = tr_val<<16;
tr_val = tr_val | command[3+2*k];
IOWR_32DIRECT(SDRAM_CONTROLLER_BASE,addr,tr_val);
addr = addr + 0x04;
}
}
}
ack_cmd[0] = ACK;
ack_cmd[1] = ACK;
ack_cmd[2] = command[3];
send_short(ack_cmd, 3);
}
else if(command[0] == CLASS_CMD)
{
q_size = 0;
q_size = command[1];
q_size = q_size<<16;
q_size = q_size | command[2];
n_dim = 0;
n_dim = command[3];
k_val = 0;
k_val = command[4];
n_load = 0;
n_load = command[5];
n_cell = 0;
n_cell = command[6];
n_cell_last = 0;
n_cell_last = command[7];
for(i = 0; i < 1;i++)
{
recv_short(command, 256);
send_short(command, 256);
}
q_addr = SDRAM_Q_ADDR_BASE;
for(i = 0;i < q_size; i++)
{
q_val = 0;
q_val = command[2*i];
q_val = q_val<<16;
q_val = q_val | command[1+2*i];
IOWR_32DIRECT(SDRAM_CONTROLLER_BASE, q_addr, q_val);
q_addr = q_addr + 0x04;
}
// set the number of dimension MAX = 256
IOWR_32DIRECT(KNNCLASSCORE_BASE, STARTCLREG,0x00000000);
IOWR_32DIRECT(BASEQADDR_0_BASE,0x00,cache_q_addr);
IOWR_32DIRECT(SKIPADDRREG_0_BASE,0x00,(q_size+1)*4);
IOWR_32DIRECT(NDIMREG_BASE,0x00,n_dim);
// number of training val in each mem
IOWR_32DIRECT(NTRREG_0_BASE,0x00,3);
IOWR_32DIRECT(NTRREG_1_BASE,0x00,3);
// k val
IOWR_32DIRECT(KNNCLASSCORE_BASE,KVALREG,k_val);
IOWR_32DIRECT(ENDTSETREG_0_BASE,0x00,0);
IOWR_32DIRECT(ENDTSETREG_1_BASE,0x00,0);
load_q_cache1 = 0;
load_q_cache0 = 0;
IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000000);
IOWR_32DIRECT(FULLREG_1_BASE,0x00,0x00000000);
PERF_RESET(PERFORMANCE_COUNTER_0_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_0_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_0_BASE,1);
IOWR_32DIRECT(KNNCLASSCORE_BASE, STARTCLREG,0x00000001);
txchan = alt_dma_txchan_open("/dev/dma");
rxchan = alt_dma_rxchan_open("/dev/dma");
alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL);
alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL);
txrx_doneCache0 = 0;
tx_data = (void*)(SDRAM_CONTROLLER_BASE+SDRAM_Q_ADDR_BASE); /* pointer to data to send */
rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_0_BASE+cache_q_addr);//CUSTOM_RAM_0_BASE
alt_dma_txchan_send (txchan,tx_data,q_size*4,NULL,NULL);
alt_dma_rxchan_prepare (rxchan,rx_buffer,q_size*4, txrxDoneCache0,NULL);
alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL);
alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL);
txrx_doneCache1 = 0;
tx_data = (void*)(SDRAM_CONTROLLER_BASE+SDRAM_Q_ADDR_BASE); /* pointer to data to send */
rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_1_BASE+cache_q_addr);//CUSTOM_RAM_0_BASE
alt_dma_txchan_send (txchan,tx_data,q_size*4,NULL,NULL);
alt_dma_rxchan_prepare (rxchan,rx_buffer,q_size*4, txrxDoneCache1,NULL);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, ledvalue);
ledvalue++;
n_load_count = 0;
memptr = 0;
IOWR_32DIRECT(KNNCLASSCORE_BASE,STARTCLREG,1); //modificato qui
//fill cache 0
empty0 = IORD_32DIRECT(EMPTYREG_0_BASE,0x00);
empty1 = IORD_32DIRECT(EMPTYREG_1_BASE,0x00);
while(txrx_doneCache1==0 || txrx_doneCache1==0);
while(n_load_count < n_load)
{
if(empty0 && (n_load_count < n_load) && txrx_doneCache0 ) // && !endmem0
{
IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000000);
IOWR_32DIRECT(ENDTSETREG_0_BASE,0x00,0);
if(n_load_count == n_load-1)
IOWR_32DIRECT(NTRREG_0_BASE, 0x00,n_cell_last/(4*(q_size+1)));
else
IOWR_32DIRECT(NTRREG_0_BASE, 0x00,n_cell/(4*(q_size+1)));
txrx_doneCache0 = 0;
alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL);
alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL);
tx_data = (void*)(SDRAM_CONTROLLER_BASE+memptr); /* pointer to data to send */
rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_0_BASE);//CUSTOM_RAM_0_BASE
if(n_load_count == n_load-1)
{
alt_dma_txchan_send (txchan,tx_data,n_cell_last,NULL,NULL);
alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell_last, txrxDoneCache0,NULL);
}
else
{
alt_dma_txchan_send (txchan,tx_data,n_cell,NULL,NULL);
alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell, txrxDoneCache0,NULL);
}
memptr = memptr + n_cell;
n_load_count++;
IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000001);
}
if(empty1 && (n_load_count< n_load) && txrx_doneCache1) // && !endmem0
{
//fill cache 1
IOWR_32DIRECT(FULLREG_1_BASE,0x00,0x00000000);
IOWR_32DIRECT(ENDTSETREG_1_BASE,0x00,0); //era 1
if(n_load_count == n_load-1)
IOWR_32DIRECT(NTRREG_1_BASE, 0x00,n_cell_last/(4*(q_size+1)));
else
IOWR_32DIRECT(NTRREG_1_BASE, 0x00,n_cell/(4*(q_size+1)));
alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL);
alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL);
txrx_doneCache1 = 0;
tx_data = (void*)(SDRAM_CONTROLLER_BASE+memptr); /* pointer to data to send */
rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_1_BASE);//CUSTOM_RAM_0_BASE
if(n_load_count == n_load-1)
{
alt_dma_txchan_send (txchan,tx_data,n_cell_last,NULL,NULL);
alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell_last, txrxDoneCache1,NULL);
}
else
{
alt_dma_txchan_send (txchan,tx_data,n_cell,NULL,NULL);
alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell, txrxDoneCache1,NULL);
}
memptr = memptr + n_cell;
n_load_count++;
IOWR_32DIRECT(FULLREG_1_BASE,0x00,0x00000001);
}
empty0 = IORD_32DIRECT(EMPTYREG_0_BASE,0x00);
empty1 = IORD_32DIRECT(EMPTYREG_1_BASE,0x00);
}
while(txrx_doneCache1==0 || txrx_doneCache1==0);
//while(empty0==0 || empty1==0);
IOWR_32DIRECT(ENDTSETREG_0_BASE,0x00,1); //era 1
IOWR_32DIRECT(ENDTSETREG_1_BASE,0x00,1); //era 1
end_class = 0;
while (!end_class)
end_class = IORD_32DIRECT(KNNCLASSCORE_BASE,ENDCLASSREG);
alt_dma_txchan_close(txchan);
alt_dma_rxchan_close(rxchan);
PERF_END(PERFORMANCE_COUNTER_0_BASE,1);
class = IORD_32DIRECT(KNNCLASSCORE_BASE,CLREG);
vote = IORD_32DIRECT(KNNCLASSCORE_BASE,NVOTREG);
count = perf_get_section_time(PERFORMANCE_COUNTER_0_BASE,1);
overflow = IORD_32DIRECT(KNNCLASSCORE_BASE,OVERFLOWREG);
command[0] = class;
command[1] = vote;
command[2] = count;
count = count>>16;
command[3] = count;
count = count>>16;
command[4] = count;
count = count>>16;
command[5] = count;
command[6] = overflow;
addr = 0;
for(i=0; i < 16; i++)
{
command[7+i] = IORD_32DIRECT(KNNCLASSCORE_BASE,addr);
addr = addr + 0x04;
}
send_short(command, 23);
}
}
int main()
{
unsigned int row = 0;
unsigned int col = 0;
unsigned int delay = 0;
unsigned int color;
int i;
// Clear the screen first.
alt_putstr("Clear the screen\n");
for (col = 0; col < FRAME_WIDTH; col = col + 4) {
for (row = 0; row < FRAME_HEIGHT; ++row) {
color = 0;
IOWR_32DIRECT(SRAM_0_BASE, row * FRAME_WIDTH + col, color << 24 | color << 16 | color << 8 | color << 0);
}
}
// Print first 16 elements of current palette
print_palette(16);
// Switch to EGA colour palette
switch_palette(&palette_ega);
print_palette(16);
alt_putstr("Screen painting demo\n");
// Cycle through the colours of the EGA colour palette
for (i = 0; i < 16; i++) {
for (delay = 0; delay < 700/*2000*/; delay++) {
unsigned int tdelay = delay;
for (tdelay; tdelay > 0; tdelay--) {}
}
for (row=0; row<480; row++) {
for (col = 0; col < 640; col=col+4) {
color = i;
IOWR_32DIRECT(SRAM_0_BASE, row * 640 + col, color << 24 | color << 16 | color << 8 | color << 0);
}
}
}
alt_putstr("\nStarting Stephen Test Pattern\n");
int p;
for (p = 0; p < palette_count; p++)
{
switch_palette(palettes[p]);
alt_putstr("Clear the screen\n");
for (col = 0; col < FRAME_WIDTH; col = col + 4) {
for (row = 0; row < FRAME_HEIGHT; row++) {
color = 0;
IOWR_32DIRECT(SRAM_0_BASE, row * FRAME_WIDTH + col, color << 24 | color << 16 | color << 8 | color << 0);
}
}
//Now draw the test pattern
for (row = 0; row < 480; row++)
{
for (col = 0; col < 640; col = col + 4)
{
color = ((row + col) % 256) << 0 | ((row + col) % 256) << 8 | ((row + col) % 256) << 16 | ((row + col) % 256) << 24;
if (row == 0 || row == 479)
{
IOWR_32DIRECT(SRAM_0_BASE, row * 640 + col, 0xFFFFFFFF);
}
else if (col == 0)
{
IOWR_32DIRECT(SRAM_0_BASE, row * 640 + col, 0x000000FF | color);
}
else if (col == 636)
{
IOWR_32DIRECT(SRAM_0_BASE, row * 640 + col, 0xFF000000 | color);
}
else
{
IOWR_32DIRECT(SRAM_0_BASE, row * 640 + col, color);
}
}
}
}
alt_putstr("Done.\n");
return 0;
}
int main()
{
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,0);// Inititialize IP core
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,1);// load GRAM command
int i;
for(i=1; i<=100; i++)
{
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,8,i);
}
while((IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,4) & 4) != 4); // wait for GRAM to finish loading
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,0);// Inititialize IP core
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,2);// load P matrix data to upper bank
alt_printf("DIN:");
for(i=1; i<=100; i++)
{
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,8,i);
DIN[i-1] = IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,8);
alt_printf("%s,", numToChar(DIN[i-1]));
}
while((IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,4) & 4) != 4); // wait for BRAM to finish loading
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,0);//Inititialize IP core
//delay(10);
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,12);// send P * G command
while((IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,4) & 8) != 8); // wait for operation to complete
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,0);//Inititialize IP core
alt_printf("\n");
IOWR_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,0,3);// offload data from lower bank. set change value to 11 to offload from upper bank
alt_printf("DOUT:\n");
char cnt = 0;
char j=0;
char offset=0;
for(i=0; i<=100; i++)
{
if (i == 0)
{IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,12);}
else
{
while((IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,4) & 32) != 32); //wait until data is ready
DOUT[i-1] = IORD_32DIRECT(MATRIX_MUL_IP_S_INT_0_BASE,12);
if(cnt == 9)
{cnt = 0;
for(j=9;j>=0;j--)
{
alt_printf("%s,", numToChar(DOUT[j+offset]));
}
alt_printf("\n\r");
offset = offset + 10;
}
else
cnt++;
}
//delay(10);
}
alt_printf("\n");
return 0;
}
