euint8 if_spi_readbuf(hwInterface *iface, euint8 *buf, euint16 len) { alt_u8 status; alt_u16 i; /* Set the SSO bit (force chipselect) */ IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_0_BASE, 0x400); /* Clear RX reg*/ buf[0] = IORD_ALTERA_AVALON_SPI_RXDATA(SPI_0_BASE); /* wait till transmit and ready ok */ do{ status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_0_BASE);//get status }while ((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 ); for(i=0;i<len;i++) { IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_0_BASE, DUMMY); /* Wait until the interface has finished transmitting */ while ((IORD_ALTERA_AVALON_SPI_STATUS(SPI_0_BASE) & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); /* reciver ready */ buf[i] = IORD_ALTERA_AVALON_SPI_RXDATA(SPI_0_BASE); } IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_0_BASE, 0); return (0); }
euint8 if_spi_sendbuf(hwInterface *iface, euint8 *buf, euint16 len) { alt_u8 SD_Data=0,status; alt_u16 i; /* Set the SSO bit (force chipselect) */ IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_0_BASE, 0x400); for(i=0;i<len;i++) { do{ status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_0_BASE);//get status }while ((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 ); /* wait till transmit and ready ok */ IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_0_BASE, buf[i]); } do{ status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_0_BASE);//get status }while ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0 ); IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_0_BASE, 0); return (0); }
euint8 if_spiSend(hwInterface *iface, euint8 outgoing) { euint8 incoming=0; alt_u8 SD_Data=0,status; /* Set the SSO bit (force chipselect) */ IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_0_BASE, 0x400); do{ status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_0_BASE);//get status }while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 ) && (status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); /* wait till transmit and ready ok */ IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_0_BASE, outgoing); /* Wait until the interface has finished transmitting */ do{status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_0_BASE);} while ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0); /* reciver ready */ if (((status & 0x80) != 0) ){ SD_Data = IORD_ALTERA_AVALON_SPI_RXDATA(SPI_0_BASE); } else{ printf("\n no recive after transmit"); } IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_0_BASE, 1); IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_0_BASE, 0); if( (status & 0x100) !=0) printf("\n error in spi error in spi"); return (SD_Data); }
int initLIS2DH12(void) { int i; alt_u16 reg_read=0xA000; alt_u16 reg_data[2]; IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_GSENSOR_BASE,0x00); //Initialize the spi control reg IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_GSENSOR_BASE, 0x2097); //setup data rate and enable x,y,z axes usleep(100*2000); IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_GSENSOR_BASE, 0x23b8); //full scale, high resolution usleep(100*2000); // Read the Device ID register IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_GSENSOR_BASE, (0x8F00)); // setup address to read from (0x0F), MSbit is R/Wn usleep(100*2000); if((IORD_ALTERA_AVALON_SPI_RXDATA(SPI_GSENSOR_BASE))!=0x33) // verify the device id matches (0x33) return -1; return 1; // success }
int alt_avalon_spi_command(alt_u32 base, alt_u32 slave, alt_u32 write_length, const alt_u8 * write_data, alt_u32 read_length, alt_u8 * read_data, alt_u32 flags) { const alt_u8 * write_end = write_data + write_length; alt_u8 * read_end = read_data + read_length; alt_u32 write_zeros = read_length; alt_u32 read_ignore = write_length; alt_u32 status; /* We must not send more than two bytes to the target before it has * returned any as otherwise it will overflow. */ /* Unfortunately the hardware does not seem to work with credits > 1, * leave it at 1 for now. */ alt_32 credits = 1; /* Warning: this function is not currently safe if called in a multi-threaded * environment, something above must perform locking to make it safe if more * than one thread intends to use it. */ IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(base, 1 << slave); /* Set the SSO bit (force chipselect) only if the toggle flag is not set */ if ((flags & ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N) == 0) { IOWR_ALTERA_AVALON_SPI_CONTROL(base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); } /* * Discard any stale data present in the RXDATA register, in case * previous communication was interrupted and stale data was left * behind. */ IORD_ALTERA_AVALON_SPI_RXDATA(base); /* Keep clocking until all the data has been processed. */ for ( ; ; ) { do { status = IORD_ALTERA_AVALON_SPI_STATUS(base); } while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 || credits == 0) && (status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); if ((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) != 0 && credits > 0) { credits--; if (write_data < write_end) IOWR_ALTERA_AVALON_SPI_TXDATA(base, *write_data++); else if (write_zeros > 0) { write_zeros--; IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0); } else credits = -1024; }; if ((status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) != 0) { alt_u32 rxdata = IORD_ALTERA_AVALON_SPI_RXDATA(base); if (read_ignore > 0) read_ignore--; else *read_data++ = (alt_u8)rxdata; credits++; if (read_ignore == 0 && read_data == read_end) break; } } /* Wait until the interface has finished transmitting */ do { status = IORD_ALTERA_AVALON_SPI_STATUS(base); } while ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0); /* Clear SSO (release chipselect) unless the caller is going to * keep using this chip */ if ((flags & ALT_AVALON_SPI_COMMAND_MERGE) == 0) IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0); return read_length; }