static void acipc_int_disable(acipc_events event)
{
IPC_ENTER();
IPCTRACE("acipc_int_disable event 0x%x\n", event);
if(event & ACIPC_INT0_EVENTS)
{
acipc->acipc_db.int0_events_cnt--;
/* for the first 8 bits we disable INTC_AC_IPC_0
* only if this is the last unbind event
*/
if (!(acipc->acipc_db.int0_events_cnt))
{
disable_irq(IRQ_ACIPC0);
}
return;
}
if (event & ACIPC_INT1_EVENTS)
{
disable_irq(IRQ_ACIPC1);
return;
}
if (event & ACIPC_INT2_EVENTS)
{
disable_irq(IRQ_ACIPC2);
return;
}
}
static void acipc_int_disable(enum acipc_events event)
{
IPC_ENTER();
IPCTRACE("acipc_int_disable event 0x%x\n", event);
if (event & ACIPC_INT0_EVENTS) {
if (!acipc->acipc_db.int0_events_cnt)
return;
acipc->acipc_db.int0_events_cnt &= ~event;
/*
* for the first 8 bits we disable INTC_AC_IPC_0
* only if this is the last unbind event
*/
if (!(acipc->acipc_db.int0_events_cnt))
disable_irq(acipc->irq[0]);
return;
}
if (event & ACIPC_INT1_EVENTS) {
disable_irq(acipc->irq[1]);
return;
}
if (event & ACIPC_INT2_EVENTS) {
disable_irq(acipc->irq[2]);
return;
}
}
static void acipc_int_enable(acipc_events event)
{
IPCTRACE("acipc_int_enable event 0x%x\n", event);
if(event & ACIPC_INT0_EVENTS)
{
/* for the first 8 bits we enable the INTC_AC_IPC_0
* only if this the first event that has been binded
*/
if (!(acipc->acipc_db.int0_events_cnt))
{
enable_irq(IRQ_ACIPC0);
}
acipc->acipc_db.int0_events_cnt++;
return;
}
if (event & ACIPC_INT1_EVENTS)
{
enable_irq(IRQ_ACIPC1);
return;
}
if (event & ACIPC_INT2_EVENTS)
{
enable_irq(IRQ_ACIPC2);
return;
}
}
static enum acipc_return_code acipc_event_set(enum acipc_events user_event)
{
IPC_ENTER();
acipc_writel_withdummy(IPC_ISRW, user_event);
IPCTRACE("acipc_event_set userEvent 0x%x\n", user_event);
IPC_LEAVE();
return ACIPC_RC_OK;
}
acipc_return_code acipc_event_set(acipc_events user_event)
{
IPC_ENTER();
acipc_writel(IPC_ISRW, user_event);
IPCTRACE("acipc_event_set userEvent 0x%x\n", user_event);
IPC_LEAVE();
return(ACIPC_RC_OK);
}
static void acipc_change_driver_state(int is_DDR_ready)
{
IPC_ENTER();
IPCTRACE("acipc_change_driver_state isDDRReady %d\n", is_DDR_ready);
if (is_DDR_ready)
acipc->acipc_db.driver_mode = ACIPC_CB_NORMAL;
else
acipc->acipc_db.driver_mode = ACIPC_CB_ALWAYS_NO_DDR;
IPC_LEAVE();
}
acipc_return_code acipc_data_send(acipc_events user_event, acipc_data data)
{
IPC_ENTER();
IPCTRACE("acipc_data_send userEvent 0x%x, data 0x%x\n", user_event, data);
/* writing the data to WDR*/
acipc_writel(IPC_WDR, data);
/* fire the event to the other subsystem
* to indicate the data is ready for read
*/
acipc_writel(IPC_ISRW, user_event);
IPC_LEAVE();
return ACIPC_RC_OK;
}
static void acipc_int_enable(enum acipc_events event)
{
IPCTRACE("acipc_int_enable event 0x%x\n", event);
if (event & ACIPC_INT0_EVENTS) {
/*
* for the first 8 bits we enable the INTC_AC_IPC_0
* only if this the first event that has been binded
*/
if (!(acipc->acipc_db.int0_events_cnt))
enable_irq(acipc->irq[0]);
acipc->acipc_db.int0_events_cnt |= event;
return;
}
if (event & ACIPC_INT1_EVENTS) {
enable_irq(acipc->irq[1]);
return;
}
if (event & ACIPC_INT2_EVENTS) {
enable_irq(acipc->irq[2]);
return;
}
}
