void idc_uart_hisr(void)
{
kal_uint16 IIR, LSR, RXTRIG;
IIR = DRV_Reg(IDC_UART_IIR);
LSR = DRV_Reg(IDC_UART_LSR);
RXTRIG = DRV_Reg(IDC_UART_RXTRIG);
if (IIR & IDC_UART_IIR_INT_INVALID)
{
IRQClearInt(MD_IRQID_IDC2ARM);
#if !defined(__UNIFIED_ISR_LEVEL__)
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return;
}
idc_hisr_time[idc_hisr_count] = DRV_Reg32(FRC_VAL_R);
idc_hisr_count++;
if (idc_hisr_count == 20)
{
idc_hisr_count = 0;
}
idc_send_rx_data_by_ilm();
if (KAL_FALSE == idc_read_RBR)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_ERROR, 0, IDC_RX_HISR_MSG, IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
#else
kal_sprintf(idc_dbg_str, "drv_idc: HISR without Read Data, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)\n\r",
IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
DT_IDC_PRINTF(idc_dbg_str);
#endif
ASSERT(0);
}
else if (((LSR & 0x9F) != 0x1) || (IIR != 0xc4))
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_ERROR, 0, IDC_RX_EXCEPTION_MSG, IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Exception occur, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)\n\r",
IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
DT_IDC_PRINTF(idc_dbg_str);
#endif
}
else if (RXTRIG == 0);
idc_read_RBR = KAL_FALSE;
IRQClearInt(MD_IRQID_IDC2ARM);
#if !defined(__UNIFIED_ISR_LEVEL__)
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return;
}
void drv_idc_init_uart(void)
{
#if defined(MT6290)
DRV_WriteReg32(BASE_ADDR_MDINFRAMISC + 0x114, DRV_Reg32(BASE_ADDR_MDINFRAMISC + 0x114) | 0x6);
DRV_WriteReg32(BASE_ADDR_MDPERIMISC + 0x114, DRV_Reg32(BASE_ADDR_MDPERIMISC + 0x114) | 0x4);
#if __FPGA__
#else
// set GPIO as default output
DRV_WriteReg32_NPW(BASE_ADDR_TOPMISC + 0x1D4, DRV_Reg32(BASE_ADDR_TOPMISC + 0x1D4) | 0x200);
#endif
#endif
#if defined(MT6595)
// Enable GPIO 29, 30 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x110, DRV_Reg32(GPIO_base + 0x110) | 0x6000);
// Select GPIO 29, 30 pull-up
DRV_WriteReg32(GPIO_base + 0x210, DRV_Reg32(GPIO_base + 0x210) | 0x6000);
#endif
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_UART_INIT_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: IDC UART Init\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
// register isr, enable RX data receive interrupt
IRQMask(MD_IRQID_IDC2ARM);
// Initialize IDC UART FIFO threshold
drv_idc_set_fifo_trigger(1);
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
DRV_WriteReg32(IDC_UART_IER, IDC_UART_IER_ERBFI);
IRQ_Register_LISR(MD_IRQID_IDC2ARM, idc_uart_lisr, "IDC_UART");
DRV_Register_HISR(DRV_IDC_HISR_ID, idc_uart_hisr);
IRQSensitivity(MD_IRQID_IDC2ARM, KAL_FALSE);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_TRUE;
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_w_ptr = 3; // 2'b11
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
// Initialize baud rate
drv_idc_set_baudrate(4000000);
// initial flags/config of IDC driver
idc_port.main_state = IDC_IN_USE;
return;
}
/*
* FUNCTION
* IMGPROC_HISR_Entry
*
* DESCRIPTION
* Hisr for image processor(stands for filter mode)
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* imgproc_dcb.state
*/
void INTERN IMGPROC_HISR_Entry(void)
{
kal_uint32 reg = DRV_Reg32(IMGPROC_INTR);
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(imgproc_dcb.mask != FILTER_NONE);
ASSERT(imgproc_dcb.state == IMGPROC_BUSY);
if(reg & IMGPROC_INTR_INT)
{
if(imgproc_dcb.cb)
imgproc_dcb.cb();
else
kal_set_eg_events(IMGPROC_Events,IMGPROC_EVENT,KAL_OR);
}
else
ASSERT(0);
imgproc_dcb.state = IMGPROC_READY;
#elif (defined(DRV_IDP_6228_SERIES))
if(reg & IMGPROC_INTR_INT)
kal_set_eg_events(IMGPROC_Events,IMGPROC_EVENT,KAL_OR);
else
ASSERT(0);
#endif
IRQClearInt(IRQ_IMGPROC_CODE);
IRQUnmask(IRQ_IMGPROC_CODE);
}
static void USB_LOGGING_DSP2_HISR(void)
{
if(log_dsp_hdlr[1] == NULL)
ASSERT(0);
log_dsp_hdlr[1]();
IRQClearInt(IRQ_IRDEBUG2_CODE);
IRQUnmask(IRQ_IRDEBUG2_CODE);
}
/*-----------------------------------------------------------------------*
*
* GPT 1us LISR function,
* pass to gpt_hw layer as a function pointer
*
*------------------------------------------------------------------------*/
DEVDRV_LS_INTSRAM_ROCODE void GPTCB_US_Lisr(kal_uint32 vector)
{
/*ASSERT( (MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER) == vector) || \
(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER) == vector) );*/
#if defined(MT6290) && defined(__ARM7EJ_S__)
IRQClearInt(vector);
#endif /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
drv_active_hisr(DRV_GPT2_HISR_ID);
}
/*-----------------------------------------------------------------------*
*
* GPT 1us LISR function,
* pass to gpt_hw layer as a function pointer
*
*------------------------------------------------------------------------*/
void GPT_DEBUG_Lisr(kal_uint32 vector)
{
/*ASSERT( (MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER) == vector) || \
(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER) == vector) );*/
#if defined(MT6290) && defined(__ARM7EJ_S__)
IRQClearInt(vector);
#endif /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
#if defined (__MTK_TARGET__) && !defined(__GPTDEBUG_HISR_DISABLE__) && defined(__LTE_RAT__)
kal_activate_hisr(gpt_debug_hisr);
#endif
}
/*
* FUNCTION
* GPT_Stop
*
* DESCRIPTION
* Stop GPT timer
*
* CALLS
* It is called to stop GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Stop(kal_uint8 timerNum)
{
kal_uint16 gpt_ctrl1;
kal_uint16 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
kal_uint16 gpt_ctrl3;
#endif
gpt_ctrl1 = DRV_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_Reg(GPT3_CTRL);
#endif
if (timerNum == 1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
if (timerNum == 2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_WriteReg(GPT3_CTRL,gpt_ctrl3);
}
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)&& (!(gpt_ctrl3&GPT3_ENABLE)))
#else
if ( ((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0 )
#endif
{
kal_uint16 GPT_Status;
GPT_Status = DRV_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
#ifdef GPT_DRVPDN_FAST
DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
}
}
/*-----------------------------------------------------------------------*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*------------------------------------------------------------------------*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_GPT_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
HGPT1_Callback();
}
if (GPT_Status & GPT_STS_2)
{
HGPT2_Callback();
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
/*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
GPTTimer.GPT_FUNC.gpt1_func();
}
if (GPT_Status & GPT_STS_2)
{
GPTTimer.GPT_FUNC.gpt2_func();
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
/*-----------------------------------------------------------------------
* FUNCTION
* GPT_DEBUG_Stop
*
* DESCRIPTION
* Remove Debug Timer Instance from queue
*
* CALLS
*
* PARAMETERS
* indx = instance number
*
* RETURNS
* None
*
*------------------------------------------------------------------------*/
static void GPT_DEBUG_Stop(kal_uint32 indx)
{
kal_uint32 savedMask;
gpt_inst *iter = &gpt_DEBUG_head;
savedMask = SaveAndSetIRQMask();
while( (iter->next!=&gpt_DEBUG_items[indx]) && (NULL!=iter->next) )
{
iter = iter->next;
}
ASSERT(NULL!=iter->next);
if(iter == &gpt_DEBUG_head)
{
kal_uint32 elapsed;
elapsed = drv_gpt_get_data(DRV_GPT_DEBUG_TIMER);
drv_gpt_stop_timer(DRV_GPT_DEBUG_TIMER);
IRQClearInt(MDGPT_INTR_ID(DRV_GPT_DEBUG_TIMER));
gpt_DEBUG_head.next = gpt_DEBUG_items[indx].next;
if(NULL != gpt_DEBUG_head.next)
{
gpt_DEBUG_head.next->ticks = gpt_DEBUG_head.next->ticks - elapsed + gpt_DEBUG_items[indx].ticks ;
drv_gpt_set_timer(DRV_GPT_DEBUG_TIMER, gpt_DEBUG_head.next->ticks, MDGPT_CTRL_MODE_ONESHOT);
drv_gpt_start_timer(DRV_GPT_DEBUG_TIMER);
}
else
{
DCL_GPT_BUS_CLOCK_TRY_OFF();
}
}
else
{
if(NULL != gpt_DEBUG_items[indx].next)
{
gpt_DEBUG_items[indx].next->ticks += gpt_DEBUG_items[indx].ticks;
}
iter->next = iter->next->next;
}
gpt_DEBUG_items[indx].next = NULL;
RestoreIRQMask(savedMask);
}
/*************************************************************************
* FUNCTION
* isrSysTimer
*
* DESCRIPTION
* This function implement CTIRQ1 LISR
*
* CALLS
*
* CALL BY
* IRQ_LISR_Init()
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
void isrSysTimer(void)
{
/* set EMI arbitrator to hard mode for GMC before running the hard real-time app */
#if defined(__DYNAMICALLY_SET_EMI_ARB_SOFT_MODE__)
EMI_Set_GMCBW_HardMode();
#endif /* __DYNAMICALLY_SET_EMI_ARB_SOFT_MODE__ */
#if !defined(__LTE_SM__)
#ifndef L1_NOT_PRESENT
L1I_FrameInterrupt();
#endif /* !L1_NOT_PRESENT */
#endif /* !defined(__LTE_SM__) */
/* restore EMI arbitrator to soft mode for GMC before running the hard real-time app */
#if defined(__DYNAMICALLY_SET_EMI_ARB_SOFT_MODE__)
EMI_Set_GMCBW_SoftMode();
#endif /* __DYNAMICALLY_SET_EMI_ARB_SOFT_MODE__ */
/* For MT6268 2G/3G or 2G Single project: timer interrupt is moved to l1csm.c for Dual/Single OS Tick mechanism */
#if !defined(__NEW_OS_TICK__) && !defined(__CENTRALIZED_SLEEP_MANAGER__)
Kal_Timer_Interrupt();
#elif (defined(__MAUI_BASIC__)||defined(__LTE_SM__)) && !defined(__CENTRALIZED_SLEEP_MANAGER__)
Kal_Timer_Interrupt();
/*KTEST: start timer tick in target full load if not event based timer!*/
#elif defined(__KTEST__) && !defined(__MAUI_BASIC__) && !defined(__CENTRALIZED_SLEEP_MANAGER__) && defined(__NEW_OS_TICK__)
Kal_Timer_Interrupt();
#endif /* !__NEW_OS_TICK__ */
#if defined(MT6290) && defined(__ARM7EJ_S__)
// need to clear pulse interrupt by driver ISR when using arm7cirq
IRQClearInt(ARM7_IRQID_MDGPTM4);
#endif /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
#ifdef FIQ
FIQClearInt();
#endif
}
/*-----------------------------------------------------------------------*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*------------------------------------------------------------------------*/
extern void GPT_MS_Time_Out_Handler(kal_uint16 *ms_handle_sta); /*defined in dcl_gpt.c*/
extern kal_uint16 gpt_ms_lisr_handle_status; /*defined in dcl_gpt.c*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_GPT_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
HGPT1_Callback();
}
if (GPT_Status & GPT_STS_2)
{
/*--------*/
//add for 1ms GPT run in LISR context
GPT_MS_Time_Out_Handler(&gpt_ms_lisr_handle_status);
HGPT2_Callback(); /* always active hisr ,here may be some optimize */
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
void USB_LOGGING_3G_HISR(void)
{
kal_uint32 buf_index;
kal_uint8 total_full_index = 0;
for(buf_index = USBACM_LOGGING_DSP_SOURCE_NUM; buf_index < USBACM_LOGGING_TOTAL_SOURCE_NUM; buf_index++)
{
total_full_index |= USB_LOGGING_Get_3G_Status((buf_index-USBACM_LOGGING_DSP_SOURCE_NUM));
}
if(total_full_index != 0)
{
if(log_3g_hdlr == NULL)
ASSERT(0);
log_3g_hdlr();
}
IRQClearInt(IRQ_LOG3G_CODE);
IRQUnmask(IRQ_LOG3G_CODE);
}
DCL_STATUS drv_idc_set_pin_config(IDC_PIN_MODE_T pin_mode)
{
DCL_STATUS return_value = STATUS_FAIL;
#if defined(MT6752) || defined(MT6735)
// IRQMask to prevent unexpected interrupt
IRQMask(MD_IRQID_IDC2ARM);
if (pin_mode == IDC_INTERNAL_PIN)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_INTERNAL_PIN_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Switch to internal pins\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
idc_port.pin_mode = IDC_INTERNAL_PIN;
// Switch to internal pins
#if defined(MT6752)
DRV_WriteReg32(GPIO_base + 0x500, DRV_Reg32(GPIO_base + 0x500) & ~(0x10));
#elif defined(MT6735)
DRV_WriteReg32(GPIO_base + 0x6D0, DRV_Reg32(GPIO_base + 0x6D0) & ~(0x20));
#endif
return_value = STATUS_OK;
}
else if (pin_mode == IDC_EXTERNAL_PIN)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_EXTERNAL_PIN_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Switch to external pins\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
idc_port.pin_mode = IDC_EXTERNAL_PIN;
// Switch to external pins
#if defined(MT6752)
DRV_WriteReg32(GPIO_base + 0x500, DRV_Reg32(GPIO_base + 0x500) | 0x10);
#elif defined(MT6735)
DRV_WriteReg32(GPIO_base + 0x6D0, DRV_Reg32(GPIO_base + 0x6D0) | 0x20);
#endif
#if defined(MT6752)
// Enable GPIO37 (PTA_TX) pull-up/pull-down
DRV_WriteReg32(IOCFG_L_BASE+0xA0, DRV_Reg32(IOCFG_L_BASE+0xA0) | 0x20);
// Select GPIO37 (PTA_TX) pull-up
DRV_WriteReg32(IOCFG_L_BASE+0xD0, DRV_Reg32(IOCFG_L_BASE+0xD0) | 0x20);
// Enable GPIO130 (PTA_RX) pull-up/pull-down
DRV_WriteReg32(IOCFG_L_BASE+0x90, DRV_Reg32(IOCFG_L_BASE+0x90) | 0x40000);
// Select GPIO130 (PTA_RX) pull-up
DRV_WriteReg32(IOCFG_L_BASE+0xC0, DRV_Reg32(IOCFG_L_BASE+0xC0) | 0x40000);
#elif defined(MT6735)
// Enable GPIO1, 2 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x930, (DRV_Reg32(GPIO_base + 0x930) | (0x3 << 24)));
// Select GPIO1, 2 pull-up
DRV_WriteReg32(GPIO_base + 0x950, (DRV_Reg32(GPIO_base + 0x950) | (0x3 << 24)));
#endif
return_value = STATUS_OK;
}
// Clear TX/RX FIFO
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return return_value;
}
void GPT_Stop_Step1(kal_uint8 timerNum)
{
register kal_uint32 gpt_ctrl1;
register kal_uint32 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
register kal_uint32 gpt_ctrl3;
#endif
#if defined(DRV_GPT_GPT4)
register kal_uint32 gpt_ctrl4;
#endif
gpt_ctrl1 = DRV_GPT_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_GPT_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_GPT_Reg(GPT3_CTRL);
#endif
#if defined(DRV_GPT_GPT4)
gpt_ctrl4 = DRV_GPT_Reg(GPT4_CTRL);
#endif
if (timerNum == 1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
else if (timerNum == 2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
else if (timerNum == 3)
{
#if !defined(GEMINI23C_EVB_BB)
GPT3_UseCount--;
if(GPT3_UseCount == 0)
{
#endif
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_GPT_WriteReg(GPT3_CTRL,gpt_ctrl3);
#if !defined(GEMINI23C_EVB_BB)
}
#endif
}
#endif //#if defined(DRV_GPT_GPT3)
#if defined(DRV_GPT_GPT4)
else if (timerNum == 4)
{
gpt_ctrl4 =(kal_uint16) ~GPT4_ENABLE;
DRV_GPT_WriteReg(GPT4_CTRL,gpt_ctrl4);
}
#endif //#if defined(DRV_GPT_GPT4)
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)
#if defined(DRV_GPT_GPT3)
&& (!(gpt_ctrl3&GPT3_ENABLE))
#endif /* defined(DRV_GPT_GPT3) */
#if defined(DRV_GPT_GPT4)
&& (!(gpt_ctrl4&GPT4_ENABLE))
#endif /* defined(DRV_GPT_GPT4) */
)
{
register kal_uint32 GPT_Status;
GPT_Status = DRV_GPT_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
}
}
/*-----------------------------------------------------------------------*
*
* It is called to stop GPT timer
*
*------------------------------------------------------------------------*/
static void GPT_Stop(kal_uint8 timerNum)
{
#if defined(DRV_GPT_STOP_2_STEP)
GPT_Stop_Step1(timerNum);
GPT_Stop_Step2();
#else
register kal_uint32 gpt_ctrl1;
register kal_uint32 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
register kal_uint32 gpt_ctrl3;
#endif
#if defined(DRV_GPT_GPT4)
register kal_uint32 gpt_ctrl4;
#endif
gpt_ctrl1 = DRV_GPT_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_GPT_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_GPT_Reg(GPT3_CTRL);
#endif
#if defined(DRV_GPT_GPT4)
gpt_ctrl4= DRV_GPT_Reg(GPT4_CTRL);
#endif
if (timerNum == GPT1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
else if (timerNum == GPT2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
else if (timerNum == GPT3)
{
#if !defined(GEMINI23C_EVB_BB)
kal_uint32 savedMask;
GPT3_UseCount--;
savedMask = SaveAndSetIRQMask();
if(GPT3_UseCount == 0)
{
#endif
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_GPT_WriteReg(GPT3_CTRL,gpt_ctrl3);
}
#if !defined(GEMINI23C_EVB_BB)
RestoreIRQMask(savedMask);
}
#endif
#endif /* defined(DRV_GPT_GPT3) */
#if defined(DRV_GPT_GPT4)
else if (timerNum == GPT4)
{
gpt_ctrl4 =(kal_uint16) ~GPT4_ENABLE;
DRV_GPT_WriteReg(GPT4_CTRL,gpt_ctrl4);
}
#endif
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)
#if defined(DRV_GPT_GPT3)
&& (!(gpt_ctrl3&GPT3_ENABLE))
#endif /* defined(DRV_GPT_GPT3) */
#if defined(DRV_GPT_GPT4)
&& (!(gpt_ctrl4&GPT4_ENABLE))
#endif /* defined(DRV_GPT_GPT4) */
)
if(KAL_TRUE==GPT_IsStop())
{
DRV_GPT_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
GPT_PDN_disable();
}
#endif //#if defined(DRV_GPT_STOP_2_STEP)
}
