/* Init and set seek LISR and HISR functions
* @param None.
* @return None
*/
void video_set_seek_isr(DECODE_TYPE decode_type)
{
kal_uint32 savedMask;
if((decode_type == DECODE_TYPE_MPEG4) || (decode_type == DECODE_TYPE_H263))
{
savedMask = SaveAndSetIRQMask();
#ifdef DRV_MP4_V1
IRQMask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQMask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
RestoreIRQMask(savedMask);
//savedMask = SaveAndSetIRQMask();
mpeg4_dec_init_isr_param();
g_mpeg4_dec_info_ptr->dec_state = MPEG4_DEC_STATE_SEEK;
#ifdef MP4_MOVE_LISR_TO_HISR
VISUAL_Register_HISR(VISUAL_MPEG4_SEEK_FIRST_HISR_ID, mpeg4_dec_seek_first_HISR);
#endif
VISUAL_Register_HISR(VISUAL_MP4_SEEK_HISR_ID, mpeg4_dec_seek_HISR);
#ifdef DRV_MP4_V1
IRQ_Register_LISR(IRQ_MPEG4_CODE, mpeg4_dec_seek_LISR, "MPEG4Seek");
IRQSensitivity(IRQ_MPEG4_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQ_Register_LISR(IRQ_MPEG4_DEC_CODE, mpeg4_dec_seek_LISR, "MPEG4Seek");
IRQSensitivity(IRQ_MPEG4_DEC_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
//RestoreIRQMask(savedMask);
}
}
void cc_irq_init()
{
kal_uint32 i;
for(i = 0; i < CC_IRQ_NUMBER; i++)
{
IRQSensitivity(CC_IRQ_INTR_ID_START + i, KAL_FALSE);
}
/* following registration cannot be placed in a for-loop for MD1 */
/* need to analyze */
IRQ_Register_LISR(CC_IRQ_INTR_ID_START, cc_irq_lisr, "CC_IRQ");
IRQ_Register_LISR(CC_IRQ_INTR_ID_START + 1, cc_irq_lisr, "CC_IRQ");
IRQ_Register_LISR(CC_IRQ_INTR_ID_START + 2, cc_irq_lisr, "CC_IRQ");
IRQ_Register_LISR(CC_IRQ_INTR_ID_START + 3, cc_irq_lisr, "CC_IRQ");
CC_IRQ_HW_INIT();
#if !defined(__UNIFIED_ISR_LEVEL__)
cc_irq_hisrid = kal_init_hisr(CC_SYS_HISR);
#endif
/* init cc sys comm */
cc_sys_comm_init();
}
void USB_LOGGING_DSP_Drv_Create_ISR(void)
{
IRQ_Register_LISR(IRQ_IRDEBUG1_CODE, USB_LOGGING_DSP1_LISR, "USB_LOGGING_DSP1");
DRV_Register_HISR(DRV_USB_LOGGING_DSP1_HISR_ID, USB_LOGGING_DSP1_HISR);
#if !defined(DRV_USB_LOGGING_V5_SINGLE_DSP)
IRQ_Register_LISR(IRQ_IRDEBUG2_CODE, USB_LOGGING_DSP2_LISR, "USB_LOGGING_DSP2");
DRV_Register_HISR(DRV_USB_LOGGING_DSP2_HISR_ID, USB_LOGGING_DSP2_HISR);
#endif
}
/*************************************************************************
* FUNCTION
* IRQ_LISR_Init
*
* DESCRIPTION
* This function implement IRQ's LISR (Low-level Interrupt Service Routine)
* Table initialization.
*
* CALLS
*
* CALL BY
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
void IRQ_LISR_Init()
{
kal_uint32 i;
for (i = NUM_IRQ_SOURCES; i != 0; i--) {
IRQ_Register_LISR(i - 1, IRQ_Default_LISR, "NULL handler");
}
/* Set CTIRQ1 handler */
IRQ_Register_LISR(IRQ_CTIRQ1_CODE, isrCTIRQ1,"CTIRQ1");
}
void drv_idc_init_uart(void)
{
#if defined(MT6290)
DRV_WriteReg32(BASE_ADDR_MDINFRAMISC + 0x114, DRV_Reg32(BASE_ADDR_MDINFRAMISC + 0x114) | 0x6);
DRV_WriteReg32(BASE_ADDR_MDPERIMISC + 0x114, DRV_Reg32(BASE_ADDR_MDPERIMISC + 0x114) | 0x4);
#if __FPGA__
#else
// set GPIO as default output
DRV_WriteReg32_NPW(BASE_ADDR_TOPMISC + 0x1D4, DRV_Reg32(BASE_ADDR_TOPMISC + 0x1D4) | 0x200);
#endif
#endif
#if defined(MT6595)
// Enable GPIO 29, 30 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x110, DRV_Reg32(GPIO_base + 0x110) | 0x6000);
// Select GPIO 29, 30 pull-up
DRV_WriteReg32(GPIO_base + 0x210, DRV_Reg32(GPIO_base + 0x210) | 0x6000);
#endif
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_UART_INIT_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: IDC UART Init\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
// register isr, enable RX data receive interrupt
IRQMask(MD_IRQID_IDC2ARM);
// Initialize IDC UART FIFO threshold
drv_idc_set_fifo_trigger(1);
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
DRV_WriteReg32(IDC_UART_IER, IDC_UART_IER_ERBFI);
IRQ_Register_LISR(MD_IRQID_IDC2ARM, idc_uart_lisr, "IDC_UART");
DRV_Register_HISR(DRV_IDC_HISR_ID, idc_uart_hisr);
IRQSensitivity(MD_IRQID_IDC2ARM, KAL_FALSE);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_TRUE;
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_w_ptr = 3; // 2'b11
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
// Initialize baud rate
drv_idc_set_baudrate(4000000);
// initial flags/config of IDC driver
idc_port.main_state = IDC_IN_USE;
return;
}
/*-----------------------------------------------------------------------
* FUNCTION
* DclSGPT_Initialize
*
* DESCRIPTION
* This function is to initialize SW GPT module.
*
* PARAMETERS
* DCL_STATUS_OK
*
* RETURNS
* none
*
*------------------------------------------------------------------------*/
DCL_STATUS DclSGPT_Initialize(void)
{
kal_uint8 index;
DCL_GPT_BUS_CLOCK_ON();
/* GPT hardware reset */
drv_gpt_reset();
IRQ_Register_LISR(MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER), GPTCB_Lisr, "GPTCBMS");
IRQ_Register_LISR(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER), GPTCB_US_Lisr, "GPTCBUS");
IRQ_Register_LISR(MDGPT_INTR_ID(DRV_GPT_DEBUG_TIMER), GPT_DEBUG_Lisr, "GPTDEBUG");
#if defined (__MTK_TARGET__) && !defined(__GPTDEBUG_HISR_DISABLE__) && defined(__LTE_RAT__)
gpt_debug_hisr = kal_init_hisr(GPT_DEBUG_HISR);
#endif
/* set gpt CB timer */
drv_gpt_set_timer(DRV_GPT_CALLBACK_TIMER, DCL_GPT_CB_TICK2US, MDGPT_CTRL_MODE_REPEAT);
/* set gpt CBUS timer */
drv_gpt_set_timer(DRV_GPT_CBUS_TIMER, DCL_GPT_CBUS_TICK2US, MDGPT_CTRL_MODE_REPEAT);
/* set gpt Debug timer, tick unit = us */
drv_gpt_set_timer(DRV_GPT_DEBUG_TIMER, DCL_GPT_CBUS_TICK2US, MDGPT_CTRL_MODE_ONESHOT);
/* set OS timer */
drv_gpt_set_timer(DRV_GPT_SYSTEM_TIMER, KAL_MICROSECS_PER_TICK, MDGPT_CTRL_MODE_REPEAT);
/* gptCB variables are initialized in BSS reset procedure */
/* Register the GPT CB HISR */
DRV_Register_HISR(DRV_GPT1_HISR_ID, GPTCB_10MS_HISR);
DRV_Register_HISR(DRV_GPT2_HISR_ID, GPTCB_US_HISR);
for (index = 0; index < MAX_GPT_ITEMS; index++)
{
gptCB_items[index].gptimer_func = GPT_ERROR_CB;
gpt_DEBUG_items[index].gptimer_func = GPT_ERROR_CB;
}
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER));
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER));
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_DEBUG_TIMER));
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_SYSTEM_TIMER));
DCL_GPT_BUS_CLOCK_OFF();
return STATUS_OK;
}
/*-----------------------------------------------------------------------*
* FUNCTION
* DclHGPT_Initialize
*
* DESCRIPTION
* This function is to initialize HW GPT module.
*
* PARAMETERS
* None
*
* RETURNS
* DCL_STATUS_OK
*
*------------------------------------------------------------------------*/
DCL_STATUS DclHGPT_Initialize(void)
{
pfHGPT1Callback = HGPT_Defaul_Callback;
pfHGPT2Callback = HGPT_Defaul_Callback;
IRQ_Register_LISR(IRQ_GPT_CODE, GPT_LISR,"GPT handler");
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
return STATUS_OK;
}
/*************************************************************************
* FUNCTION
* IRQ_LISR_Init
*
* DESCRIPTION
* This function implement IRQ's LISR (Low-level Interrupt Service Routine)
* Table initialization.
*
* CALLS
*
* CALL BY
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
void IRQ_LISR_Init()
{
#if !defined(__UNIFIED_ISR_LEVEL__)
kal_uint32 i;
for (i = NUM_IRQ_SOURCES; i != 0; i--) {
IRQ_Register_LISR(i - 1, IRQ_Default_LISR, "NULL handler");
}
#endif /* __UNIFIED_ISR_LEVEL__ */
/* Set CTIRQ1 handler */
#if !defined(L1_NOT_PRESENT) && !defined(ATEST_DRV_ENVIRON)
IRQ_Register_LISR(IRQ_CTIRQ1_CODE, isrCTIRQ1,"CTIRQ1");
#endif/* L1_NOT_PRESENT */
/* Set system timer handler */
#if !defined(__EVENT_BASED_TIMER__)
IRQ_Register_LISR(IRQ_SYS_TIMER_CODE, isrSysTimer,"SysTimer");
#endif /* __EVENT_BASED_TIMER__ */
}
/*
* FUNCTION
* IMGPROC_Init
*
* DESCRIPTION
* Initialize the IMGPROC driver and it should be called only once.
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
kal_int32 API IMGPROC_Init(void)
{
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(IMGPROC_Events == 0);
IMGPROC_Events = kal_create_event_group("IMGPROC Events");
VISUAL_Register_HISR(VISUAL_IMGPROC_HISR_ID,IMGPROC_HISR_Entry);
IRQ_Register_LISR(IRQ_IMGPROC_CODE, IMGPROC_LISR_Entry,"IMGPROC");
IRQSensitivity(IRQ_IMGPROC_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_IMGPROC_CODE);
kal_mem_set(&imgproc_dcb,0,sizeof(IMGPROC_DCB_STRUCT));
#elif (defined(DRV_IDP_6228_SERIES))
IMGPROC_Events = kal_create_event_group("IMGPROC Events");
VISUAL_Register_HISR(VISUAL_IMGPROC_HISR_ID,IMGPROC_HISR_Entry);
IRQ_Register_LISR(IRQ_IMGPROC_CODE, IMGPROC_LISR_Entry,"IMGPROC");
IRQSensitivity(IRQ_IMGPROC_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_IMGPROC_CODE);
#endif
return NO_ERROR;
}
/*************************************************************************
* FUNCTION
* mdci_init
*
* DESCRIPTION
* This function initialized MDIF.
*
* PARAMETERS
* arb - arbitration mode flag
* md_offset - modem side master offset address(in bytes).
*
* RETURNS
* none
*
*************************************************************************/
void mdci_hw_init(kal_uint32 arb, kal_uint32 md_offset)
{
/* set arbitration mode */
if (arb == 1) {
*MDIF_CON |= MDIF_CON_ARB;
}
/* initialize the MD side address offset */
mdci_md_offset = md_offset;
/* register LISR */
#if defined(MDIF_FOR_AP_SIDE)
IRQ_Register_LISR(IRQ_APMDIF_CODE, mdci_lisr, "MDIF LISR");
#else
IRQ_Register_LISR(IRQ_MDIF_CODE, mdci_lisr, "MDIF LISR");
#endif
#ifndef __IVP__
/* register HISR */
DRV_Register_HISR(DRV_MDIF_HISR_ID, mdci_hisr);
#endif /* __IVP__ */
/* set IRQ sensitivity */
#if defined(MDIF_FOR_AP_SIDE)
IRQSensitivity(IRQ_APMDIF_CODE, LEVEL_SENSITIVE);
#else
IRQSensitivity(IRQ_MDIF_CODE, LEVEL_SENSITIVE);
#endif
/* unmask MDIF */
#if defined(MDIF_FOR_AP_SIDE)
IRQUnmask(IRQ_APMDIF_CODE);
#else
IRQUnmask(IRQ_MDIF_CODE);
#endif
}
/*************************************************************************
* FUNCTION
* ccif_init
*
* DESCRIPTION
* This function initialized EMIMPU.
*
* PARAMETERS
* none
*
* RETURNS
* none
*
*************************************************************************/
void emimpu_init(kal_uint32 arb, kal_uint32 md_offset)
{
/* register LISR */
IRQ_Register_LISR(IRQ_EMI_CODE, emimpu_lisr, "EMIMPU LISR");
/* register HISR */
/* set IRQ sensitivity */
IRQSensitivity(IRQ_EMI_CODE, LEVEL_SENSITIVE);
/* unmask EMIMPU */
IRQUnmask(IRQ_EMI_CODE);
}
void
idp_imgdma_init(void)
{
#ifndef MDP_C_MODEL
#if defined(IDP_FULL_ISR_SUPPORT)
IRQ_Register_LISR(IRQ_ROT_DMA_CODE, idp_imgdma_LISR, "IMGDMA");
#endif
IRQSensitivity(IRQ_ROT_DMA_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_ROT_DMA_CODE);
#endif // #ifndef MDP_C_MODEL
// Initial the owner structure.
idp_imgdma_rotdma0_init();
}
/*
* FUNCTION
* GPT_init
*
* DESCRIPTION
* GPT initial function
*
* CALLS
* Initialize the GPT module
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
* GPT_Callback = callback function, called when GPT intr. is coming
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_init(kal_uint8 timerNum, void (*GPT_Callback)(void))
{
IRQ_Register_LISR(IRQ_GPT_CODE, GPT_LISR,"GPT handler");
if (timerNum == 1)
{
GPTTimer.GPT_FUNC.gpt1_func = GPT_Callback;
GPT_clock(1,clk_1k);
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
}
if (timerNum == 2)
{
GPTTimer.GPT_FUNC.gpt2_func = GPT_Callback;
GPT_clock(2,clk_16k);
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
}
}
void i2c_init(void)
{
//kal_uint32 savedMask;
i2c_status.state=SCCB_READY_STATE;
//savedMask = SaveAndSetIRQMask();
/* Switch GPIO to HW Mode */
//GPIO_ModeSetup(SCCB_SERIAL_CLK_PIN,SCCB_GPIO_SCL_MODE);
//GPIO_ModeSetup(SCCB_SERIAL_DATA_PIN,SCCB_GPIO_SDA_MODE);
//RestoreIRQMask(savedMask);
IRQ_Register_LISR(IRQ_I2C_CODE, i2c_lisr,"I2C ISR");
IRQUnmask(IRQ_I2C_CODE);
ENABLE_I2C_ACK_ERR_DET; //Always enable ack error detection
ENABLE_I2C_NAKERR_DET; //Always enable nack error detection
#if (defined(SCCB_DMA_ENABLED))
i2c_status.is_DMA_enabled=KAL_FALSE;
#endif
}
void hif_init(void)
{
// Init structure.
memset(hif_internal_handle, 0, sizeof(hif_internal_handle));
#if defined (HIF0_CHANNEL_SUPPORT)
// Init HIF interrupr
IRQ_Register_LISR(IRQ_HIF_CODE, hif0_lisr, "HIF0 ISR");
IRQSensitivity(IRQ_HIF_CODE, LEVEL_SENSITIVE);
//hif_hisr_id[0] = kal_create_hisr("HIF0_HISR", 0, 1024, hif0_hisr, KAL_TRUE);
DRV_Register_HISR(DRV_HIF0_HISR_ID, hif0_hisr);
IRQUnmask(IRQ_HIF_CODE);
#endif
#if defined (HIF1_CHANNEL_SUPPORT)
IRQ_Register_LISR(IRQ_HIF_1_CODE, hif1_lisr, "HIF1 ISR");
IRQSensitivity(IRQ_HIF_1_CODE, LEVEL_SENSITIVE);
//hif_hisr_id[1] = kal_create_hisr("HIF1_HISR", 0, 1024, hif1_hisr, KAL_TRUE);
DRV_Register_HISR(DRV_HIF1_HISR_ID, hif1_hisr);
IRQUnmask(IRQ_HIF_1_CODE);
#endif
/* DMA initialization */
#if defined (HIF0_CHANNEL_SUPPORT)
hif_sysdma_id[0] = DMA_GetChannel(DMA_HIF0);
hif_dma_menu[0].TMOD.burst_mode = KAL_FALSE;
hif_dma_menu[0].master = DMA_HIF0;
hif_dma_menu[0].addr = 0;
#endif
#if defined (HIF1_CHANNEL_SUPPORT)
hif_sysdma_id[1] = DMA_GetChannel(DMA_HIF1);
hif_dma_menu[1].TMOD.burst_mode = KAL_FALSE;
hif_dma_menu[1].master = DMA_HIF1;
hif_dma_menu[1].addr = 0;
#endif
// Configure DMA
//hif_dma_input.size = DMA_SHORT;
hif_dma_input[0].count = 0;
hif_dma_input[0].callback = NULL;
hif_dma_input[1].count = 0;
hif_dma_input[1].callback = NULL;
//hif_dma_input.menu = (void*) &hif_dma_menu;
//define ECO solution for MT6256E4,MT6575E2, MT6255E2 or MTK later chips
#if defined(MT6255) || defined(MT6256)//MT6255 and MT6256 support query chip version
chip_version = INT_SW_SecVersion(); //Query chip version
#endif
#if defined(__AST_TL1_TDD__) //HIF ECO only support for TDD project
#if defined(MT6575_S01)
hif_eco_support = KAL_FALSE;
#elif defined(MT6752)
hif_eco_support = KAL_TRUE;
#elif defined(MT6255) //MT6255E2 support HIF ECO
if(SW_SEC_0 != chip_version)
{
hif_eco_support = KAL_TRUE;
}
#elif defined(MT6256) //MT6256E4,MT6256E5 support HIF ECO
if(SW_SEC_1 == chip_version) //SW_SEC_0: MT6256E2,E3,E4, SW_SEC_1: MT6256E5
{
hif_eco_support = KAL_TRUE;
}
#endif
#endif
hif_events = kal_create_event_group("HIFDrv");
}
void EINT_Registration(kal_uint8 eintno, kal_bool Dbounce_En, kal_bool ACT_Polarity, \
void (reg_hisr)(void), kal_bool auto_umask)
{
kal_uint32 savedMask;
kal_uint16 count;
EXT_ASSERT(eintno < EINT_TOTAL_CHANNEL, eintno, Dbounce_En, ACT_Polarity);
IRQ_Register_LISR(IRQ_EIT_CODE, EINT_LISR, "EINT handler");
/* Save and set MCU's I,F bits to disable interrupts */
savedMask = LockIRQ();
/* Set external interrupt polarity */
if (ACT_Polarity)
EINTaddr(eintno) |= EINT_CON_HIGHLEVEL;
else
EINTaddr(eintno) &= ~(EINT_CON_HIGHLEVEL);
/*
* NoteXXX: Only EINT 0 ~ (EINT_MAX_CHANNLE - 1) support level trigger.
* The de-bounce time is only for level trigger EINT.
*/
if (eintno < EINT_MAX_CHANNEL) {
/* Set external interrupt debounce control enable or not */
if (Dbounce_En) {
/* check if debounce is enabled */
if (EINTaddr(eintno) & EINT_CON_DEBOUNCE_EN) {
/* debounce value is already set; NOP */
} else {
EINTaddr(eintno) |= (EINT_CON_DEBOUNCE | EINT_CON_DEBOUNCE_EN);
}
}
else
{
/*disable debounce */
EINTaddr(eintno) &= ~(EINT_CON_DEBOUNCE_EN);
}
}
/* Register external interrupt's HISR */
EINT_FUNC.eint_func[eintno] = reg_hisr;
EINT_FUNC.eint_active[eintno] = KAL_FALSE;
EINT_FUNC.eint_auto_umask[eintno] = auto_umask;
/* register HISR */
DRV_Register_HISR(DRV_EINT_HISR_ID, EINT_HISR_Entry);
/* Restore previous MCU's I,F bits setting */
RestoreIRQ(savedMask);
/*
* XXX!!!. Hardware bug
* - must wait for 32khz/1 sec to write mask register, will be
* fixed in future.
*/
for (count=0; count<250; count++) ; /*250:52M*/
savedMask = LockIRQ();
*EINT_INTACK = EINT_INTACK_EINT(eintno);
#if defined(MT6205) || defined(MT6208) || defined(FPGA)
*EINT_MASK &= ~(0x0001 << eintno);
#else
*EINT_MASK_CLR = (0x0001 << eintno);
#endif
RestoreIRQ(savedMask);
/* Set external interrupt is level sensitive */
#if !defined(__DIRECTION_SENSOR_SUPPORT__)
if( (0)
#if defined(__DIRECTION_SENSOR_SUPPORT__)
|| eintno == MOTION_SENSOR_EINT_NO1
|| eintno == MOTION_SENSOR_EINT_NO2
#endif
)
{
IRQSensitivity(IRQ_EIT_CODE,EDGE_SENSITIVE);
}else{
IRQSensitivity(IRQ_EIT_CODE,LEVEL_SENSITIVE);
}
#endif
/* Enable external interrupt */
IRQUnmask(IRQ_EIT_CODE);
}
void EINT_Registration_and_mask(kal_uint8 eintno, kal_bool Dbounce_En, kal_bool ACT_Polarity, void (reg_hisr)(void), kal_bool auto_umask)
{
// PDN_CLR(PDN_GPIO);
kal_uint32 savedMask;
/* If EINT Number is out of range, get return address and send it to exception handler */
if(eintno >= EINT_TOTAL_CHANNEL)
{
kal_uint32 retaddr;
GET_RETURN_ADDRESS(retaddr);
kal_fatal_error_handler(KAL_ERROR_DRV_EINT_INVALID_INDEX, retaddr);
}
/*disable eint interrupt*/
eint_set_irqen(eintno, EINT_DISABLE);
/*register LISR*/
/*dispatch for dedicated eint*/
if (eint_is_dedicated & (1<<eintno))
{
switch(eint_is_dedicated_map[eintno])
{
case DEDICATED_EINT0:
{
eint_set_l1_eint_enable(DEDICATED_EINT0, EINT_DISABLE);
IRQ_Register_LISR(DEDICATED_EINT_IRQ0, DEINT0_LISR, "DEINT0 handler");
}
break;
case DEDICATED_EINT1:
{
eint_set_l1_eint_enable(DEDICATED_EINT1, EINT_DISABLE);
IRQ_Register_LISR(DEDICATED_EINT_IRQ1, DEINT1_LISR, "DEINT1 handler");
}
break;
case DEDICATED_EINT2:
{
eint_set_l1_eint_enable(DEDICATED_EINT2, EINT_DISABLE);
IRQ_Register_LISR(DEDICATED_EINT_IRQ2, DEINT2_LISR, "DEINT2 handler");
}
break;
case DEDICATED_EINT3:
{
eint_set_l1_eint_enable(DEDICATED_EINT3, EINT_DISABLE);
IRQ_Register_LISR(DEDICATED_EINT_IRQ3, DEINT3_LISR, "DEINT3 handler");
}
break;
default:
break;
}
}
else
{
IRQ_Register_LISR(IRQ_EIT_CODE, EINT_LISR, "EINT handler");
}
/* Save and set MCU's I,F bits to disable interrupts */
// savedMask = LockIRQ();
/* Set external interrupt polarity */
EINT_Set_Polarity(eintno,ACT_Polarity);
#if !defined(MT6290)
gpio_set_eint_src(eintno,eint_src_map[eintno]);
#endif
if (Dbounce_En)
{
//eint_set_debounce_duration(eintno,EINT_DB_DUR_DEFAULT);
eint_set_debounce_enable(eintno,EINT_ENABLE);
}
else
{
/*disable debounce */
eint_set_debounce_enable(eintno,EINT_DISABLE);
}
/* Save and set MCU's I,F bits to disable interrupts */
savedMask = SaveAndSetIRQMask();
/* Register external interrupt's HISR */
EINT_FUNC.eint_func[eintno] = reg_hisr;
EINT_FUNC.eint_active[eintno] = KAL_FALSE;
EINT_FUNC.eint_auto_umask[eintno] = auto_umask;
if (eint_is_dedicated & (1<<eintno))
{
/* register HISR */
DRV_Register_HISR(DRV_DEINT_HISR_ID, DEINT_HISR_Entry);
EINT_L2_ACK(eintno);
//EINT_UnMask(eintno);
RestoreIRQMask(savedMask);
}
else
{
/* register HISR */
DRV_Register_HISR(DRV_EINT_HISR_ID, EINT_HISR_Entry);
EINT_L2_ACK(eintno);
//EINT_UnMask(eintno);
IRQSensitivity( IRQ_EIT_CODE, LEVEL_SENSITIVE );
/* Enable external interrupt */
IRQUnmask( IRQ_EIT_CODE );
RestoreIRQMask(savedMask);
}
}
