/* Check pitch constriants for all chips & tiling formats */
bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
int tile_width;
/* Linear is always fine */
if (tiling_mode == I915_TILING_NONE)
return true;
if (!IS_I9XX(dev) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
tile_width = 128;
else
tile_width = 512;
/* check maximum stride & object size */
if (IS_I965G(dev)) {
/* i965 stores the end address of the gtt mapping in the fence
* reg, so dont bother to check the size */
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
return false;
} else if (IS_GEN3(dev) || IS_GEN2(dev)) {
if (stride > 8192)
return false;
if (IS_GEN3(dev)) {
if (size > I830_FENCE_MAX_SIZE_VAL << 20)
return false;
} else {
if (size > I830_FENCE_MAX_SIZE_VAL << 19)
return false;
}
}
/* 965+ just needs multiples of tile width */
if (IS_I965G(dev)) {
if (stride & (tile_width - 1))
return false;
return true;
}
/* Pre-965 needs power of two tile widths */
if (stride < tile_width)
return false;
if (stride & (stride - 1))
return false;
return true;
}
/* Is the current GTT allocation valid for the change in tiling? */
static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
{
u32 size;
if (tiling_mode == I915_TILING_NONE)
return true;
if (INTEL_INFO(obj->base.dev)->gen >= 4)
return true;
if (IS_GEN3(obj->base.dev)) {
if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
return false;
} else {
if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
return false;
}
size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
if (i915_gem_obj_ggtt_size(obj) != size)
return false;
if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
return false;
return true;
}
BOOL copybox3d_supported()
{
#if defined(GMA_USECOPY3D)
// supported chipsets
if( IS_GEN3( sd->ProductID ) )
{
return TRUE;
}
#endif
return FALSE;
}
static GLboolean
intelCreateContext(gl_api api,
const struct gl_config * mesaVis,
__DRIcontext * driContextPriv,
unsigned major_version,
unsigned minor_version,
uint32_t flags,
bool notify_reset,
unsigned *error,
void *sharedContextPrivate)
{
bool success = false;
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->driverPrivate;
if (flags & ~__DRI_CTX_FLAG_DEBUG) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
return false;
}
if (notify_reset) {
*error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
return false;
}
if (IS_GEN3(intelScreen->deviceID)) {
success = i915CreateContext(api, mesaVis, driContextPriv,
major_version, minor_version, flags,
error, sharedContextPrivate);
} else {
intelScreen->no_vbo = true;
success = i830CreateContext(api, mesaVis, driContextPriv,
major_version, minor_version, flags,
error, sharedContextPrivate);
}
if (success)
return true;
if (driContextPriv->driverPrivate != NULL)
intelDestroyContext(driContextPriv);
return false;
}
static bool stride_is_valid(struct drm_i915_private *dev_priv,
unsigned int stride)
{
/* These should have been caught earlier. */
WARN_ON(stride < 512);
WARN_ON((stride & (64 - 1)) != 0);
/* Below are the additional FBC restrictions. */
if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
return stride == 4096 || stride == 8192;
if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
return false;
if (stride > 16384)
return false;
return true;
}
static void render_copyfunc(struct scratch_buf *src, unsigned src_x, unsigned src_y,
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y,
unsigned logical_tile_no)
{
if (IS_GEN2(devid))
gen2_render_copyfunc(src, src_x, src_y,
dst, dst_x, dst_y,
logical_tile_no);
else if (IS_GEN3(devid))
gen3_render_copyfunc(src, src_x, src_y,
dst, dst_x, dst_y,
logical_tile_no);
else if (IS_GEN6(devid))
gen6_render_copyfunc(src, src_x, src_y,
dst, dst_x, dst_y,
logical_tile_no);
else
blitter_copyfunc(src, src_x, src_y,
dst, dst_x, dst_y,
logical_tile_no);
}
Bool intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
int limit;
/* 8xx spec has always 8K limit, but tests show larger limit in
non-tiling mode, which makes large monitor work. */
if (tiling) {
if (IS_GEN2(intel))
limit = KB(8);
else if (IS_GEN3(intel))
limit = KB(8);
else if (IS_GEN4(intel))
limit = KB(16);
else
limit = KB(32);
} else
limit = KB(32);
return stride <= limit;
}
/**
* Returns the fence size for a tiled area of the given size.
*/
unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size)
{
unsigned long i;
unsigned long start;
if (INTEL_INFO(intel)->gen >= 040 || intel->has_relaxed_fencing) {
/* The 965 can have fences at any page boundary. */
return ALIGN(size, 4096);
} else {
/* Align the size to a power of two greater than the smallest fence
* size.
*/
if (IS_GEN3(intel))
start = MB(1);
else
start = KB(512);
for (i = start; i < size; i <<= 1) ;
return i;
}
}
/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
int tile_width, tile_height;
/* Linear is always fine */
if (tiling_mode == I915_TILING_NONE)
return true;
if (IS_GEN2(dev) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
tile_width = 128;
else
tile_width = 512;
/* check maximum stride & object size */
if (INTEL_INFO(dev)->gen >= 4) {
/* i965 stores the end address of the gtt mapping in the fence
* reg, so dont bother to check the size */
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
return false;
} else {
if (stride > 8192)
return false;
if (IS_GEN3(dev)) {
if (size > I830_FENCE_MAX_SIZE_VAL << 20)
return false;
} else {
if (size > I830_FENCE_MAX_SIZE_VAL << 19)
return false;
}
}
if (IS_GEN2(dev) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
tile_height = 32;
else
tile_height = 8;
/* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even
* number of tile rows. */
if (IS_GEN2(dev))
tile_height *= 2;
/* Size needs to be aligned to a full tile row */
if (size & (tile_height * stride - 1))
return false;
/* 965+ just needs multiples of tile width */
if (INTEL_INFO(dev)->gen >= 4) {
if (stride & (tile_width - 1))
return false;
return true;
}
/* Pre-965 needs power of two tile widths */
if (stride < tile_width)
return false;
if (stride & (stride - 1))
return false;
return true;
}
/**
* Detects bit 6 swizzling of address lookup between IGD access and CPU
* access through main memory.
*/
void
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
if (INTEL_INFO(dev)->gen >= 6) {
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (IS_GEN5(dev)) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
} else if (IS_GEN2(dev)) {
/* As far as we know, the 865 doesn't have these bit 6
* swizzling issues.
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
uint32_t dcc;
/* On 9xx chipsets, channel interleave by the CPU is
* determined by DCC. For single-channel, neither the CPU
* nor the GPU do swizzling. For dual channel interleaved,
* the GPU's interleave is bit 9 and 10 for X tiled, and bit
* 9 for Y tiled. The CPU's interleave is independent, and
* can be based on either bit 11 (haven't seen this yet) or
* bit 17 (common).
*/
dcc = I915_READ(DCC);
switch (dcc & DCC_ADDRESSING_MODE_MASK) {
case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
break;
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
if (dcc & DCC_CHANNEL_XOR_DISABLE) {
/* This is the base swizzling by the GPU for
* tiled buffers.
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
/* Bit 11 swizzling by the CPU in addition. */
swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
swizzle_y = I915_BIT_6_SWIZZLE_9_11;
} else {
/* Bit 17 swizzling by the CPU in addition. */
swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
swizzle_y = I915_BIT_6_SWIZZLE_9_17;
}
break;
}
if (dcc == 0xffffffff) {
DRM_ERROR("Couldn't read from MCHBAR. "
"Disabling tiling.\n");
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
}
} else {
/* The 965, G33, and newer, have a very flexible memory
* configuration. It will enable dual-channel mode
* (interleaving) on as much memory as it can, and the GPU
* will additionally sometimes enable different bit 6
* swizzling for tiled objects from the CPU.
*
* Here's what I found on the G965:
* slot fill memory size swizzling
* 0A 0B 1A 1B 1-ch 2-ch
* 512 0 0 0 512 0 O
* 512 0 512 0 16 1008 X
* 512 0 0 512 16 1008 X
* 0 512 0 512 16 1008 X
* 1024 1024 1024 0 2048 1024 O
*
* We could probably detect this based on either the DRB
* matching, which was the case for the swizzling required in
* the table above, or from the 1-ch value being less than
* the minimum size of a rank.
*/
if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else {
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
}
}
dev_priv->mm.bit_6_swizzle_x = swizzle_x;
dev_priv->mm.bit_6_swizzle_y = swizzle_y;
}
/**
* Detects bit 6 swizzling of address lookup between IGD access and CPU
* access through main memory.
*/
void
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
/*
* On BDW+, swizzling is not used. We leave the CPU memory
* controller in charge of optimizing memory accesses without
* the extra address manipulation GPU side.
*
* VLV and CHV don't have GPU swizzling.
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (INTEL_INFO(dev)->gen >= 6) {
uint32_t dimm_c0, dimm_c1;
dimm_c0 = I915_READ(MAD_DIMM_C0);
dimm_c1 = I915_READ(MAD_DIMM_C1);
dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
/* Enable swizzling when the channels are populated with
* identically sized dimms. We don't need to check the 3rd
* channel because no cpu with gpu attached ships in that
* configuration. Also, swizzling only makes sense for 2
* channels anyway. */
if (dimm_c0 == dimm_c1) {
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
} else {
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
} else if (IS_GEN5(dev)) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
} else if (IS_GEN2(dev)) {
/* As far as we know, the 865 doesn't have these bit 6
* swizzling issues.
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
uint32_t dcc;
/* On 9xx chipsets, channel interleave by the CPU is
* determined by DCC. For single-channel, neither the CPU
* nor the GPU do swizzling. For dual channel interleaved,
* the GPU's interleave is bit 9 and 10 for X tiled, and bit
* 9 for Y tiled. The CPU's interleave is independent, and
* can be based on either bit 11 (haven't seen this yet) or
* bit 17 (common).
*/
dcc = I915_READ(DCC);
switch (dcc & DCC_ADDRESSING_MODE_MASK) {
case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
break;
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
if (dcc & DCC_CHANNEL_XOR_DISABLE) {
/* This is the base swizzling by the GPU for
* tiled buffers.
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
/* Bit 11 swizzling by the CPU in addition. */
swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
swizzle_y = I915_BIT_6_SWIZZLE_9_11;
} else {
/* Bit 17 swizzling by the CPU in addition. */
swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
swizzle_y = I915_BIT_6_SWIZZLE_9_17;
}
break;
}
if (dcc == 0xffffffff) {
DRM_ERROR("Couldn't read from MCHBAR. "
"Disabling tiling.\n");
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
}
} else {
/* The 965, G33, and newer, have a very flexible memory
* configuration. It will enable dual-channel mode
* (interleaving) on as much memory as it can, and the GPU
* will additionally sometimes enable different bit 6
* swizzling for tiled objects from the CPU.
*
* Here's what I found on the G965:
* slot fill memory size swizzling
* 0A 0B 1A 1B 1-ch 2-ch
* 512 0 0 0 512 0 O
* 512 0 512 0 16 1008 X
* 512 0 0 512 16 1008 X
* 0 512 0 512 16 1008 X
* 1024 1024 1024 0 2048 1024 O
*
* We could probably detect this based on either the DRB
* matching, which was the case for the swizzling required in
* the table above, or from the 1-ch value being less than
* the minimum size of a rank.
*/
if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else {
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
}
}
dev_priv->mm.bit_6_swizzle_x = swizzle_x;
dev_priv->mm.bit_6_swizzle_y = swizzle_y;
}
int main(int argc, char **argv)
{
uint32_t *handle, *start_val;
uint32_t start = 0;
int i, fd, count;
igt_simple_init(argc, argv);
fd = drm_open_any();
igt_require(IS_GEN3(intel_get_drm_devid(fd)));
count = 0;
if (argc > 1)
count = atoi(argv[1]);
if (count == 0)
count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
igt_info("Using %d 1MiB buffers\n", count);
handle = malloc(sizeof(uint32_t)*count*2);
start_val = handle + count;
for (i = 0; i < count; i++) {
handle[i] = create_bo(fd, start);
start_val[i] = start;
start += 1024 * 1024 / 4;
}
igt_info("Verifying initialisation...\n");
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
igt_info("Cyclic blits, forward...\n");
for (i = 0; i < count * 4; i++) {
int src = i % count;
int dst = (i + 1) % count;
copy(fd, handle[dst], handle[src]);
start_val[dst] = start_val[src];
}
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
igt_info("Cyclic blits, backward...\n");
for (i = 0; i < count * 4; i++) {
int src = (i + 1) % count;
int dst = i % count;
copy(fd, handle[dst], handle[src]);
start_val[dst] = start_val[src];
}
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
igt_info("Random blits...\n");
for (i = 0; i < count * 4; i++) {
int src = random() % count;
int dst = random() % count;
if (src == dst)
continue;
copy(fd, handle[dst], handle[src]);
start_val[dst] = start_val[src];
}
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
igt_exit();
}
int main(int argc, char **argv)
{
uint32_t *handle, *tiling, *start_val;
uint32_t start = 0;
int i, fd, count;
fd = drm_open_any();
if (!IS_GEN3(intel_get_drm_devid(fd))) {
printf("gen3-only test, doing nothing\n");
return 77;
}
count = 0;
if (argc > 1)
count = atoi(argv[1]);
if (count == 0)
count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
printf("Using %d 1MiB buffers\n", count);
handle = malloc(sizeof(uint32_t)*count*3);
tiling = handle + count;
start_val = tiling + count;
for (i = 0; i < count; i++) {
handle[i] = create_bo(fd, start, tiling[i] = i % 3);
start_val[i] = start;
start += 1024 * 1024 / 4;
}
printf("Verifying initialisation..."); fflush(stdout);
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
printf("done\n");
printf("Cyclic blits, forward..."); fflush(stdout);
for (i = 0; i < count * 32; i++) {
int src = i % count;
int dst = (i + 1) % count;
copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
start_val[dst] = start_val[src];
}
printf("verifying..."); fflush(stdout);
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
printf("done\n");
printf("Cyclic blits, backward..."); fflush(stdout);
for (i = 0; i < count * 32; i++) {
int src = (i + 1) % count;
int dst = i % count;
copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
start_val[dst] = start_val[src];
}
printf("verifying..."); fflush(stdout);
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
printf("done\n");
printf("Random blits..."); fflush(stdout);
for (i = 0; i < count * 32; i++) {
int src = random() % count;
int dst = random() % count;
while (src == dst)
dst = random() % count;
copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
start_val[dst] = start_val[src];
}
printf("verifying..."); fflush(stdout);
for (i = 0; i < count; i++)
check_bo(fd, handle[i], start_val[i]);
printf("done\n");
return 0;
}
static void parse_options(int argc, char **argv)
{
int c, tmp;
int option_index = 0;
static struct option long_options[] = {
{"no-hw", 0, 0, 'd'},
{"buf-size", 1, 0, 's'},
{"gpu-busy-load", 1, 0, 'g'},
{"no-signals", 0, 0, 'S'},
{"buffer-count", 1, 0, 'c'},
{"trace-tile", 1, 0, 't'},
{"disable-blt", 0, 0, 'b'},
{"disable-render", 0, 0, 'r'},
{"untiled", 0, 0, 'u'},
{"x-tiled", 0, 0, 'x'},
{"use-cpu-maps", 0, 0, 'm'},
{"rounds", 1, 0, 'o'},
{"no-fail", 0, 0, 'f'},
{"tiles-per-buf", 0, 0, 'p'},
#define DUCTAPE 0xdead0001
{"remove-duct-tape", 0, 0, DUCTAPE},
#define TILESZ 0xdead0002
{"tile-size", 1, 0, TILESZ},
#define CHCK_RENDER 0xdead0003
{"check-render-cpyfn", 0, 0, CHCK_RENDER},
};
options.scratch_buf_size = 256*4096;
options.no_hw = 0;
options.use_signal_helper = 1;
options.gpu_busy_load = 0;
options.num_buffers = 0;
options.trace_tile = -1;
options.use_render = 1;
options.use_blt = 1;
options.forced_tiling = -1;
options.use_cpu_maps = 0;
options.total_rounds = 512;
options.fail = 1;
options.ducttape = 1;
options.tile_size = 16;
options.tiles_per_buf = options.scratch_buf_size / TILE_BYTES(options.tile_size);
options.check_render_cpyfn = 0;
while((c = getopt_long(argc, argv, "ds:g:c:t:rbuxmo:fp:",
long_options, &option_index)) != -1) {
switch(c) {
case 'd':
options.no_hw = 1;
printf("no-hw debug mode\n");
break;
case 'S':
options.use_signal_helper = 0;
printf("disabling that pesky nuisance who keeps interrupting us\n");
break;
case 's':
tmp = atoi(optarg);
if (tmp < options.tile_size*8192)
printf("scratch buffer size needs to be at least %i\n",
options.tile_size*8192);
else if (tmp & (tmp - 1)) {
printf("scratch buffer size needs to be a power-of-two\n");
} else {
printf("fixed scratch buffer size to %u\n", tmp);
options.scratch_buf_size = tmp;
sanitize_tiles_per_buf();
}
break;
case 'g':
tmp = atoi(optarg);
if (tmp < 0 || tmp > 10)
printf("gpu busy load needs to be bigger than 0 and smaller than 10\n");
else {
printf("gpu busy load factor set to %i\n", tmp);
gpu_busy_load = options.gpu_busy_load = tmp;
}
break;
case 'c':
options.num_buffers = atoi(optarg);
printf("buffer count set to %i\n", options.num_buffers);
break;
case 't':
options.trace_tile = atoi(optarg);
printf("tracing tile %i\n", options.trace_tile);
break;
case 'r':
options.use_render = 0;
printf("disabling render copy\n");
break;
case 'b':
options.use_blt = 0;
printf("disabling blt copy\n");
break;
case 'u':
options.forced_tiling = I915_TILING_NONE;
printf("disabling tiling\n");
break;
case 'x':
if (options.use_cpu_maps) {
printf("tiling not possible with cpu maps\n");
} else {
options.forced_tiling = I915_TILING_X;
printf("using only X-tiling\n");
}
break;
case 'm':
options.use_cpu_maps = 1;
options.forced_tiling = I915_TILING_NONE;
printf("disabling tiling\n");
break;
case 'o':
options.total_rounds = atoi(optarg);
printf("total rounds %i\n", options.total_rounds);
break;
case 'f':
options.fail = 0;
printf("not failing when detecting errors\n");
break;
case 'p':
options.tiles_per_buf = atoi(optarg);
printf("tiles per buffer %i\n", options.tiles_per_buf);
break;
case DUCTAPE:
options.ducttape = 0;
printf("applying duct-tape\n");
break;
case TILESZ:
options.tile_size = atoi(optarg);
sanitize_tiles_per_buf();
printf("til size %i\n", options.tile_size);
break;
case CHCK_RENDER:
options.check_render_cpyfn = 1;
printf("checking render copy function\n");
break;
default:
printf("unkown command options\n");
break;
}
}
if (optind < argc)
printf("unkown command options\n");
/* actually 32767, according to docs, but that kills our nice pot calculations. */
options.max_dimension = 16*1024;
if (options.use_render) {
if (IS_GEN2(devid) || IS_GEN3(devid))
options.max_dimension = 2048;
else
options.max_dimension = 8192;
}
printf("Limiting buffer to %dx%d\n",
options.max_dimension, options.max_dimension);
}
void
init_instdone_definitions(uint32_t devid)
{
if (IS_GEN7(devid)) {
init_gen7_instdone();
} else if (IS_GEN6(devid)) {
/* Now called INSTDONE_1 in the docs. */
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 3");
gen6_instdone1_bit(GEN6_EU_32_DONE, "EU 32");
gen6_instdone1_bit(GEN6_EU_31_DONE, "EU 31");
gen6_instdone1_bit(GEN6_EU_30_DONE, "EU 30");
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 2");
gen6_instdone1_bit(GEN6_EU_22_DONE, "EU 22");
gen6_instdone1_bit(GEN6_EU_21_DONE, "EU 21");
gen6_instdone1_bit(GEN6_EU_20_DONE, "EU 20");
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 1");
gen6_instdone1_bit(GEN6_EU_12_DONE, "EU 12");
gen6_instdone1_bit(GEN6_EU_11_DONE, "EU 11");
gen6_instdone1_bit(GEN6_EU_10_DONE, "EU 10");
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 0");
gen6_instdone1_bit(GEN6_EU_02_DONE, "EU 02");
gen6_instdone1_bit(GEN6_EU_01_DONE, "EU 01");
gen6_instdone1_bit(GEN6_EU_00_DONE, "EU 00");
gen6_instdone1_bit(GEN6_IC_3_DONE, "IC 3");
gen6_instdone1_bit(GEN6_IC_2_DONE, "IC 2");
gen6_instdone1_bit(GEN6_IC_1_DONE, "IC 1");
gen6_instdone1_bit(GEN6_IC_0_DONE, "IC 0");
gen6_instdone1_bit(GEN6_ISC_10_DONE, "ISC 1/0");
gen6_instdone1_bit(GEN6_ISC_32_DONE, "ISC 3/2");
gen6_instdone1_bit(GEN6_VSC_DONE, "VSC");
gen6_instdone1_bit(GEN6_IEF_DONE, "IEF");
gen6_instdone1_bit(GEN6_VFE_DONE, "VFE");
gen6_instdone1_bit(GEN6_TD_DONE, "TD");
gen6_instdone1_bit(GEN6_TS_DONE, "TS");
gen6_instdone1_bit(GEN6_GW_DONE, "GW");
gen6_instdone1_bit(GEN6_HIZ_DONE, "HIZ");
gen6_instdone1_bit(GEN6_AVS_DONE, "AVS");
/* Now called INSTDONE_2 in the docs. */
gen6_instdone2_bit(GEN6_GAM_DONE, "GAM");
gen6_instdone2_bit(GEN6_CS_DONE, "CS");
gen6_instdone2_bit(GEN6_WMBE_DONE, "WMBE");
gen6_instdone2_bit(GEN6_SVRW_DONE, "SVRW");
gen6_instdone2_bit(GEN6_RCC_DONE, "RCC");
gen6_instdone2_bit(GEN6_SVG_DONE, "SVG");
gen6_instdone2_bit(GEN6_ISC_DONE, "ISC");
gen6_instdone2_bit(GEN6_MT_DONE, "MT");
gen6_instdone2_bit(GEN6_RCPFE_DONE, "RCPFE");
gen6_instdone2_bit(GEN6_RCPBE_DONE, "RCPBE");
gen6_instdone2_bit(GEN6_VDI_DONE, "VDI");
gen6_instdone2_bit(GEN6_RCZ_DONE, "RCZ");
gen6_instdone2_bit(GEN6_DAP_DONE, "DAP");
gen6_instdone2_bit(GEN6_PSD_DONE, "PSD");
gen6_instdone2_bit(GEN6_IZ_DONE, "IZ");
gen6_instdone2_bit(GEN6_WMFE_DONE, "WMFE");
gen6_instdone2_bit(GEN6_SVSM_DONE, "SVSM");
gen6_instdone2_bit(GEN6_QC_DONE, "QC");
gen6_instdone2_bit(GEN6_FL_DONE, "FL");
gen6_instdone2_bit(GEN6_SC_DONE, "SC");
gen6_instdone2_bit(GEN6_DM_DONE, "DM");
gen6_instdone2_bit(GEN6_FT_DONE, "FT");
gen6_instdone2_bit(GEN6_DG_DONE, "DG");
gen6_instdone2_bit(GEN6_SI_DONE, "SI");
gen6_instdone2_bit(GEN6_SO_DONE, "SO");
gen6_instdone2_bit(GEN6_PL_DONE, "PL");
gen6_instdone2_bit(GEN6_VME_DONE, "VME");
gen6_instdone2_bit(GEN6_SF_DONE, "SF");
gen6_instdone2_bit(GEN6_CL_DONE, "CL");
gen6_instdone2_bit(GEN6_GS_DONE, "GS");
gen6_instdone2_bit(GEN6_VS0_DONE, "VS0");
gen6_instdone2_bit(GEN6_VF_DONE, "VF");
} else if (IS_GEN5(devid)) {
gen4_instdone_bit(ILK_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(ILK_ROW_0_EU_1_DONE, "Row 0, EU 1");
gen4_instdone_bit(ILK_ROW_0_EU_2_DONE, "Row 0, EU 2");
gen4_instdone_bit(ILK_ROW_0_EU_3_DONE, "Row 0, EU 3");
gen4_instdone_bit(ILK_ROW_1_EU_0_DONE, "Row 1, EU 0");
gen4_instdone_bit(ILK_ROW_1_EU_1_DONE, "Row 1, EU 1");
gen4_instdone_bit(ILK_ROW_1_EU_2_DONE, "Row 1, EU 2");
gen4_instdone_bit(ILK_ROW_1_EU_3_DONE, "Row 1, EU 3");
gen4_instdone_bit(ILK_ROW_2_EU_0_DONE, "Row 2, EU 0");
gen4_instdone_bit(ILK_ROW_2_EU_1_DONE, "Row 2, EU 1");
gen4_instdone_bit(ILK_ROW_2_EU_2_DONE, "Row 2, EU 2");
gen4_instdone_bit(ILK_ROW_2_EU_3_DONE, "Row 2, EU 3");
gen4_instdone_bit(ILK_VCP_DONE, "VCP");
gen4_instdone_bit(ILK_ROW_0_MATH_DONE, "Row 0 math");
gen4_instdone_bit(ILK_ROW_1_MATH_DONE, "Row 1 math");
gen4_instdone_bit(ILK_ROW_2_MATH_DONE, "Row 2 math");
gen4_instdone_bit(ILK_VC1_DONE, "VC1");
gen4_instdone_bit(ILK_ROW_0_MA_DONE, "Row 0 MA");
gen4_instdone_bit(ILK_ROW_1_MA_DONE, "Row 1 MA");
gen4_instdone_bit(ILK_ROW_2_MA_DONE, "Row 2 MA");
gen4_instdone_bit(ILK_ROW_0_ISC_DONE, "Row 0 ISC");
gen4_instdone_bit(ILK_ROW_1_ISC_DONE, "Row 1 ISC");
gen4_instdone_bit(ILK_ROW_2_ISC_DONE, "Row 2 ISC");
gen4_instdone_bit(ILK_VFE_DONE, "VFE");
gen4_instdone_bit(ILK_TD_DONE, "TD");
gen4_instdone_bit(ILK_SVTS_DONE, "SVTS");
gen4_instdone_bit(ILK_TS_DONE, "TS");
gen4_instdone_bit(ILK_GW_DONE, "GW");
gen4_instdone_bit(ILK_AI_DONE, "AI");
gen4_instdone_bit(ILK_AC_DONE, "AC");
gen4_instdone_bit(ILK_AM_DONE, "AM");
init_g4x_instdone1();
} else if (IS_GEN4(devid)) {
gen4_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1");
gen4_instdone_bit(I965_ROW_0_EU_2_DONE, "Row 0, EU 2");
gen4_instdone_bit(I965_ROW_0_EU_3_DONE, "Row 0, EU 3");
gen4_instdone_bit(I965_ROW_1_EU_0_DONE, "Row 1, EU 0");
gen4_instdone_bit(I965_ROW_1_EU_1_DONE, "Row 1, EU 1");
gen4_instdone_bit(I965_ROW_1_EU_2_DONE, "Row 1, EU 2");
gen4_instdone_bit(I965_ROW_1_EU_3_DONE, "Row 1, EU 3");
gen4_instdone_bit(I965_SF_DONE, "Strips and Fans");
gen4_instdone_bit(I965_SE_DONE, "Setup Engine");
gen4_instdone_bit(I965_WM_DONE, "Windowizer");
gen4_instdone_bit(I965_DISPATCHER_DONE, "Dispatcher");
gen4_instdone_bit(I965_PROJECTION_DONE, "Projection and LOD");
gen4_instdone_bit(I965_DG_DONE, "Dependent address generator");
gen4_instdone_bit(I965_QUAD_CACHE_DONE, "Texture fetch");
gen4_instdone_bit(I965_TEXTURE_FETCH_DONE, "Texture fetch");
gen4_instdone_bit(I965_TEXTURE_DECOMPRESS_DONE, "Texture decompress");
gen4_instdone_bit(I965_SAMPLER_CACHE_DONE, "Sampler cache");
gen4_instdone_bit(I965_FILTER_DONE, "Filtering");
gen4_instdone_bit(I965_BYPASS_DONE, "Bypass FIFO");
gen4_instdone_bit(I965_PS_DONE, "Pixel shader");
gen4_instdone_bit(I965_CC_DONE, "Color calculator");
gen4_instdone_bit(I965_MAP_FILTER_DONE, "Map filter");
gen4_instdone_bit(I965_MAP_L2_IDLE, "Map L2");
gen4_instdone_bit(I965_MA_ROW_0_DONE, "Message Arbiter row 0");
gen4_instdone_bit(I965_MA_ROW_1_DONE, "Message Arbiter row 1");
gen4_instdone_bit(I965_IC_ROW_0_DONE, "Instruction cache row 0");
gen4_instdone_bit(I965_IC_ROW_1_DONE, "Instruction cache row 1");
gen4_instdone_bit(I965_CP_DONE, "Command Processor");
if (IS_G4X(devid)) {
init_g4x_instdone1();
} else {
init_g965_instdone1();
}
} else if (IS_GEN3(devid)) {
gen3_instdone_bit(IDCT_DONE, "IDCT");
gen3_instdone_bit(IQ_DONE, "IQ");
gen3_instdone_bit(PR_DONE, "PR");
gen3_instdone_bit(VLD_DONE, "VLD");
gen3_instdone_bit(IP_DONE, "Instruction parser");
gen3_instdone_bit(FBC_DONE, "Framebuffer Compression");
gen3_instdone_bit(BINNER_DONE, "Binner");
gen3_instdone_bit(SF_DONE, "Strips and fans");
gen3_instdone_bit(SE_DONE, "Setup engine");
gen3_instdone_bit(WM_DONE, "Windowizer");
gen3_instdone_bit(IZ_DONE, "Intermediate Z");
gen3_instdone_bit(PERSPECTIVE_INTERP_DONE, "Perspective interpolation");
gen3_instdone_bit(DISPATCHER_DONE, "Dispatcher");
gen3_instdone_bit(PROJECTION_DONE, "Projection and LOD");
gen3_instdone_bit(DEPENDENT_ADDRESS_DONE, "Dependent address calculation");
gen3_instdone_bit(TEXTURE_FETCH_DONE, "Texture fetch");
gen3_instdone_bit(TEXTURE_DECOMPRESS_DONE, "Texture decompression");
gen3_instdone_bit(SAMPLER_CACHE_DONE, "Sampler Cache");
gen3_instdone_bit(FILTER_DONE, "Filtering");
gen3_instdone_bit(BYPASS_FIFO_DONE, "Bypass FIFO");
gen3_instdone_bit(PS_DONE, "Pixel shader");
gen3_instdone_bit(CC_DONE, "Color calculator");
gen3_instdone_bit(MAP_FILTER_DONE, "Map filter");
gen3_instdone_bit(MAP_L2_IDLE, "Map L2");
} else {
assert(IS_GEN2(devid));
gen3_instdone_bit(I830_GMBUS_DONE, "GMBUS");
gen3_instdone_bit(I830_FBC_DONE, "FBC");
gen3_instdone_bit(I830_BINNER_DONE, "BINNER");
gen3_instdone_bit(I830_MPEG_DONE, "MPEG");
gen3_instdone_bit(I830_MECO_DONE, "MECO");
gen3_instdone_bit(I830_MCD_DONE, "MCD");
gen3_instdone_bit(I830_MCSTP_DONE, "MCSTP");
gen3_instdone_bit(I830_CC_DONE, "CC");
gen3_instdone_bit(I830_DG_DONE, "DG");
gen3_instdone_bit(I830_DCMP_DONE, "DCMP");
gen3_instdone_bit(I830_FTCH_DONE, "FTCH");
gen3_instdone_bit(I830_IT_DONE, "IT");
gen3_instdone_bit(I830_MG_DONE, "MG");
gen3_instdone_bit(I830_MEC_DONE, "MEC");
gen3_instdone_bit(I830_PC_DONE, "PC");
gen3_instdone_bit(I830_QCC_DONE, "QCC");
gen3_instdone_bit(I830_TB_DONE, "TB");
gen3_instdone_bit(I830_WM_DONE, "WM");
gen3_instdone_bit(I830_EF_DONE, "EF");
gen3_instdone_bit(I830_BLITTER_DONE, "Blitter");
gen3_instdone_bit(I830_MAP_L2_DONE, "Map L2 cache");
gen3_instdone_bit(I830_SECONDARY_RING_3_DONE, "Secondary ring 3");
gen3_instdone_bit(I830_SECONDARY_RING_2_DONE, "Secondary ring 2");
gen3_instdone_bit(I830_SECONDARY_RING_1_DONE, "Secondary ring 1");
gen3_instdone_bit(I830_SECONDARY_RING_0_DONE, "Secondary ring 0");
gen3_instdone_bit(I830_PRIMARY_RING_1_DONE, "Primary ring 1");
gen3_instdone_bit(I830_PRIMARY_RING_0_DONE, "Primary ring 0");
}
}
int
i915_load_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
ret = intel_parse_bios(dev);
if (ret)
DRM_INFO("failed to find VBIOS tables\n");
#if 0
intel_register_dsm_handler();
#endif
/* IIR "flip pending" bit means done if this bit is set */
if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
dev_priv->flip_pending_is_done = true;
#ifdef notyet
ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
if (ret)
goto cleanup_vga_client;
/* Initialise stolen first so that we may reserve preallocated
* objects for the BIOS to KMS transition.
*/
ret = i915_gem_init_stolen(dev);
if (ret)
goto cleanup_vga_switcheroo;
#endif
intel_modeset_init(dev);
ret = i915_gem_init(dev);
if (ret)
goto cleanup_gem_stolen;
intel_modeset_gem_init(dev);
ret = drm_irq_install(dev);
if (ret)
goto cleanup_gem;
/* Always safe in the mode setting case. */
/* FIXME: do pre/post-mode set stuff in core KMS code */
dev->vblank_disable_allowed = 1;
ret = intel_fbdev_init(dev);
if (ret)
goto cleanup_irq;
drm_kms_helper_poll_init(dev);
/* We're off and running w/KMS */
dev_priv->mm.suspended = 0;
return (0);
cleanup_irq:
drm_irq_uninstall(dev);
cleanup_gem:
DRM_LOCK();
i915_gem_cleanup_ringbuffer(dev);
DRM_UNLOCK();
i915_gem_cleanup_aliasing_ppgtt(dev);
cleanup_gem_stolen:
#ifdef notyet
i915_gem_cleanup_stolen(dev);
#endif
return (ret);
}
