RTMP_BUILD_DRV_OPS_FUNCTION_BODY
#endif /* OS_ABL_FUNC_SUPPORT */
#endif /* LINUX */
int rt28xx_init(
IN VOID *pAdSrc,
IN PSTRING pDefaultMac,
IN PSTRING pHostName)
{
PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc;
UINT index;
UCHAR TmpPhy;
NDIS_STATUS Status;
if (pAd == NULL)
return FALSE;
#ifdef CONFIG_STA_SUPPORT
#ifdef PCIE_PS_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
/* If dirver doesn't wake up firmware here,*/
/* NICLoadFirmware will hang forever when interface is up again.*/
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) &&
OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
{
AUTO_WAKEUP_STRUC AutoWakeupCfg;
AsicForceWakeup(pAd, TRUE);
AutoWakeupCfg.word = 0;
RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
}
}
#endif /* PCIE_PS_SUPPORT */
#endif /* CONFIG_STA_SUPPORT */
/* reset Adapter flags*/
RTMP_CLEAR_FLAGS(pAd);
/* Init BssTab & ChannelInfo tabbles for auto channel select.*/
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
AutoChBssTableInit(pAd);
ChannelInfoInit(pAd);
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef DOT11_N_SUPPORT
/* Allocate BA Reordering memory*/
if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE)
goto err1;
#endif /* DOT11_N_SUPPORT */
/* Make sure MAC gets ready.*/
index = 0;
if (WaitForAsicReady(pAd) != TRUE)
goto err1;
DBGPRINT(RT_DEBUG_TRACE, ("MAC[Ver:Rev=0x%08x]\n", pAd->MACVersion));
if (MAX_LEN_OF_MAC_TABLE > MAX_AVAILABLE_CLIENT_WCID(pAd))
{
DBGPRINT(RT_DEBUG_ERROR, ("MAX_LEN_OF_MAC_TABLE can not be larger than MAX_AVAILABLE_CLIENT_WCID!!!!\n"));
goto err1;
}
#ifdef RTMP_MAC_PCI
/* To fix driver disable/enable hang issue when radio off*/
RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2);
#endif /* RTMP_MAC_PCI */
/* Disable DMA*/
RT28XXDMADisable(pAd);
/* Load 8051 firmware*/
Status = NICLoadFirmware(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status));
goto err1;
}
NICLoadRateSwitchingParams(pAd);
/* Disable interrupts here which is as soon as possible*/
/* This statement should never be true. We might consider to remove it later*/
#ifdef RTMP_MAC_PCI
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
{
RTMP_ASIC_INTERRUPT_DISABLE(pAd);
}
#endif /* RTMP_MAC_PCI */
#ifdef RESOURCE_PRE_ALLOC
Status = RTMPInitTxRxRingMemory(pAd);
#else
Status = RTMPAllocTxRxRingMemory(pAd);
#endif /* RESOURCE_PRE_ALLOC */
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status));
goto err2;
}
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
/* initialize MLME*/
#ifdef RT6352
pAd->bCalibrationDone = FALSE;
#endif /* RT6352 */
Status = RtmpMgmtTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err3;
Status = MlmeInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status));
goto err4;
}
#ifdef RMTP_RBUS_SUPPORT
#ifdef VIDEO_TURBINE_SUPPORT
VideoConfigInit(pAd);
#endif /* VIDEO_TURBINE_SUPPORT */
#endif /* RMTP_RBUS_SUPPORT */
/* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default*/
UserCfgInit(pAd);
Status = RtmpNetTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err5;
/* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr);*/
/* pAd->bForcePrintTX = TRUE;*/
CfgInitHook(pAd);
#ifdef CONFIG_AP_SUPPORT
if ((pAd->OpMode == OPMODE_AP)
#ifdef P2P_SUPPORT
|| TRUE
#endif /* P2P_SUPPORT */
)
APInitialize(pAd);
#endif /* CONFIG_AP_SUPPORT */
#ifdef BLOCK_NET_IF
initblockQueueTab(pAd);
#endif /* BLOCK_NET_IF */
Status = MeasureReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
Status = TpcReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
/* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset*/
Status = NICInitializeAdapter(pAd, TRUE);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status));
if (Status != NDIS_STATUS_SUCCESS)
goto err6;
}
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
}
#endif /* CONFIG_AP_SUPPORT */
/* Read parameters from Config File */
/* unknown, it will be updated in NICReadEEPROMParameters */
pAd->RfIcType = RFIC_UNKNOWN;
Status = RTMPReadParametersHook(pAd);
if(pAd->CommonCfg.Channel==0)
{
RTMPSetDefaultChannel(pAd);
}
#ifdef CONFIG_STA_SUPPORT
#ifdef CREDENTIAL_STORE
RecoverConnectInfo(pAd);
#endif /* CREDENTIAL_STORE */
#endif /* CONFIG_STA_SUPPORT */
DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status));
goto err6;
}
#ifdef DOT11_N_SUPPORT
/*Init Ba Capability parameters.*/
/* RT28XX_BA_INIT(pAd);*/
pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable;
pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
/* UPdata to HT IE*/
pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
#endif /* DOT11_N_SUPPORT */
/* after reading Registry, we now know if in AP mode or STA mode*/
/* Load 8051 firmware; crash when FW image not existent*/
/* Status = NICLoadFirmware(pAd);*/
/* if (Status != NDIS_STATUS_SUCCESS)*/
/* break;*/
DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
/* We should read EEPROM for all cases. rt2860b*/
NICReadEEPROMParameters(pAd, (PSTRING)pDefaultMac);
#ifdef CONFIG_STA_SUPPORT
#endif /* CONFIG_STA_SUPPORT */
DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
#ifdef LED_CONTROL_SUPPORT
/* Send LED Setting to MCU */
RTMPInitLEDMode(pAd);
#endif /* LED_CONTROL_SUPPORT */
NICInitAsicFromEEPROM(pAd); /* rt2860b */
#ifdef RT6352
if (IS_RT6352(pAd))
{
RtmpKickOutHwNullFrame(pAd, TRUE, FALSE);
#if defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT)
{
ULONG SysRegValue;
RTMP_SYS_IO_READ32(0xb0000060, &SysRegValue);
if ((SysRegValue & 0x100000) == 0x0)
{
SysRegValue |= 0x100000;
RTMP_SYS_IO_WRITE32(0xb0000060, SysRegValue);
DBGPRINT(RT_DEBUG_ERROR,("Change as GPIO Mode(0x%x)\n", SysRegValue));
}
}
#endif /* defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT) */
/* Do R-Calibration */
R_Calibration(pAd);
#ifdef RTMP_TEMPERATURE_CALIBRATION
/* Temperature Init */
RT6352_Temperature_Init(pAd);
RT6352_TemperatureCalibration(pAd);
#endif /* RTMP_TEMPERATURE_CALIBRATION */
#ifdef RTMP_TEMPERATURE_COMPENSATION
/*
read out tempature reference value (0x80 ~ 0x7F)
TssiPlusBoundaryG [7] [6] [5] [4] [3] [2] [1] [0] (smaller) +
TssiMinusBoundaryG[0] [1] [2] [3] [4] [5] [6] [7] (larger)
*/
RT6352_EEPROM_TSSI_24G_READ(pAd);
/*
pAd->TssiCalibratedOffset:
reference temperature(e2p[D1h])
*/
/* adjust the boundary table by pAd->TssiCalibratedOffset */
RT6352_TssiTableAdjust(pAd);
/* ATE temperature(e2p[77h]) */
RT6352_TssiMpAdjust(pAd);
DBGPRINT(RT_DEBUG_OFF,("E2PROM: G Tssi[-7 .. +7] = %d %d %d %d %d %d %d - %d - %d %d %d %d %d %d %d, offset=%d, tuning=%d\n",
pAd->TssiMinusBoundaryG[7], pAd->TssiMinusBoundaryG[6], pAd->TssiMinusBoundaryG[5],
pAd->TssiMinusBoundaryG[4], pAd->TssiMinusBoundaryG[3], pAd->TssiMinusBoundaryG[2], pAd->TssiMinusBoundaryG[1],
pAd->TssiRefG,
pAd->TssiPlusBoundaryG[1], pAd->TssiPlusBoundaryG[2], pAd->TssiPlusBoundaryG[3], pAd->TssiPlusBoundaryG[4],
pAd->TssiPlusBoundaryG[5], pAd->TssiPlusBoundaryG[6], pAd->TssiPlusBoundaryG[7],
pAd->TssiCalibratedOffset, pAd->bAutoTxAgcG));
#endif /* RTMP_TEMPERATURE_COMPENSATION */
AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, TRUE);
AsicLockChannel(pAd, pAd->CommonCfg.Channel);
/* RF Self TX DC Calibration */
RF_SELF_TXDC_CAL(pAd);
/* Rx DCOC Calibration */
RxDCOC_Calibration(pAd);
/* BandWidth Filter Calibration */
BW_Filter_Calibration(pAd,TRUE);
BW_Filter_Calibration(pAd,FALSE);
/* Do LOFT and IQ Calibration */
LOFT_IQ_Calibration(pAd);
/* DPD_Calibration */
#ifdef RT6352_EP_SUPPORT
if (pAd->bExtPA == FALSE)
#endif /* RT6352_EP_SUPPORT */
{
DoDPDCalibration(pAd);
pAd->DoDPDCurrTemperature = 0x7FFFFFFF;
}
/* Rx DCOC Calibration */
RxDCOC_Calibration(pAd);
/* Do RXIQ Calibration */
RXIQ_Calibration(pAd);
#if defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT)
RT6352_Init_ExtPA_ExtLNA(pAd, FALSE);
#endif /* defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT) */
}
#endif /* RT6352 */
#ifdef RALINK_ATE
if (ATEInit(pAd) != NDIS_STATUS_SUCCESS)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s(): ATE initialization failed !\n", __FUNCTION__));
goto err6;
}
#endif /* RALINK_ATE */
#ifdef RTMP_INTERNAL_TX_ALC
/* Initialize the desired TSSI table*/
RTMP_CHIP_ASIC_TSSI_TABLE_INIT(pAd);
#endif /* RTMP_INTERNAL_TX_ALC */
InitRfPaModeTable(pAd);
#ifdef RTMP_TEMPERATURE_COMPENSATION
/* Temperature compensation, initialize the lookup table */
DBGPRINT(RT_DEBUG_OFF, ("bAutoTxAgcG = %d\n", pAd->bAutoTxAgcG));
if (pAd->chipCap.bTempCompTxALC && pAd->bAutoTxAgcG)
InitLookupTable(pAd);
#endif /* RTMP_TEMPERATURE_COMPENSATION */
/* Set PHY to appropriate mode*/
TmpPhy = pAd->CommonCfg.PhyMode;
pAd->CommonCfg.PhyMode = 0xff;
RTMPSetPhyMode(pAd, TmpPhy);
#ifdef DOT11_N_SUPPORT
SetCommonHT(pAd);
#endif /* DOT11_N_SUPPORT */
/* No valid channels.*/
if (pAd->ChannelListNum == 0)
{
DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n"));
goto err6;
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0],
pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2],
pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4]));
#endif /* DOT11_N_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef AP_QLOAD_SUPPORT
/* init QBSS Element */
QBSS_LoadInit(pAd);
#endif /* AP_QLOAD_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
/* APInitialize(pAd);*/
#ifdef IKANOS_VX_1X0
VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress);
#endif /* IKANOS_VX_1X0 */
#ifdef RALINK_ATE
#endif /* RALINK_ATE */
#ifdef CONFIG_AP_SUPPORT
/* Initialize RF register to default value*/
if (pAd->OpMode == OPMODE_AP)
{
AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
AsicLockChannel(pAd, pAd->CommonCfg.Channel);
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef RTMP_INTERNAL_TX_ALC
#ifdef RT6352
if (IS_RT6352(pAd) && (pAd->TxPowerCtrl.bInternalTxALC == TRUE))
{
RT635xTssiDcCalibration(pAd);
}
#endif /* RT6352 */
#endif /* RTMP_INTERNAL_TX_ALC */
/*
Some modules init must be called before APStartUp().
Or APStartUp() will make up beacon content and call
other modules API to get some information to fill.
*/
if (pAd && (Status != NDIS_STATUS_SUCCESS))
{
/* Undo everything if it failed*/
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE))
{
/* NdisMDeregisterInterrupt(&pAd->Interrupt);*/
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
}
/* RTMPFreeAdapter(pAd); we will free it in disconnect()*/
}
else if (pAd)
{
/* Microsoft HCT require driver send a disconnect event after driver initialization.*/
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
OPSTATUS_CLEAR_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE);
DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n"));
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
if (pAd->ApCfg.bAutoChannelAtBootup || (pAd->CommonCfg.Channel == 0))
{
UINT8 BBPValue = 0;
/* Enable Interrupt first due to we need to scan channel to receive beacons.*/
RTMP_IRQ_ENABLE(pAd);
/* Now Enable RxTx*/
RTMPEnableRxTx(pAd);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP);
/* Let BBP register at 20MHz to do scan */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
BBPValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
DBGPRINT(RT_DEBUG_ERROR, ("SYNC - BBP R4 to 20MHz.l\n"));
/* Now we can receive the beacon and do the listen beacon*/
/* use default BW to select channel*/
pAd->CommonCfg.Channel = AP_AUTO_CH_SEL(pAd, pAd->ApCfg.AutoChannelAlg);
pAd->ApCfg.bAutoChannelAtBootup = FALSE;
}
#ifdef DOT11_N_SUPPORT
/* If phymode > PHY_11ABGN_MIXED and BW=40 check extension channel, after select channel */
N_ChannelCheck(pAd);
#ifdef DOT11N_DRAFT3
/*
We only do this Overlapping BSS Scan when system up, for the
other situation of channel changing, we depends on station's
report to adjust ourself.
*/
if (pAd->CommonCfg.bForty_Mhz_Intolerant == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Disable 20/40 BSSCoex Channel Scan(BssCoex=%d, 40MHzIntolerant=%d)\n",
pAd->CommonCfg.bBssCoexEnable,
pAd->CommonCfg.bForty_Mhz_Intolerant));
}
else if(pAd->CommonCfg.bBssCoexEnable == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Enable 20/40 BSSCoex Channel Scan(BssCoex=%d)\n",
pAd->CommonCfg.bBssCoexEnable));
APOverlappingBSSScan(pAd);
}
RTMP_11N_D3_TimerInit(pAd);
/* RTMPInitTimer(pAd, &pAd->CommonCfg.Bss2040CoexistTimer, GET_TIMER_FUNCTION(Bss2040CoexistTimeOut), pAd, FALSE);*/
#endif /* DOT11N_DRAFT3 */
#endif /* DOT11_N_SUPPORT */
APStartUp(pAd);
DBGPRINT(RT_DEBUG_OFF, ("Main bssid = %02x:%02x:%02x:%02x:%02x:%02x\n",
PRINT_MAC(pAd->ApCfg.MBSSID[BSS0].Bssid)));
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef RT6352
pAd->bCalibrationDone = TRUE;
if (IS_RT6352(pAd))
{
#ifdef DYNAMIC_VGA_SUPPORT
if (pAd->CommonCfg.MO_Cfg.bDyncVGAEnable)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R195, 0x83);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R196, 0x70);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R195, 0x86);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R196, 0x70);
}
#endif /* DYNAMIC_VGA_SUPPORT */
}
#endif /* RT6352 */
}/* end of else*/
/* Set up the Mac address*/
#ifdef CONFIG_AP_SUPPORT
#ifndef P2P_APCLI_SUPPORT
RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], NULL);
#endif /* P2P_APCLI_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
#ifdef CONFIG_STA_SUPPORT
RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], (PUCHAR)(pAd->StaCfg.dev_name));
#endif /* CONFIG_STA_SUPPORT */
/* Various AP function init*/
#ifdef CONFIG_AP_SUPPORT
#ifdef P2P_SUPPORT
#else
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
#endif /* P2P_SUPPORT */
{
#ifdef MBSS_SUPPORT
/* the function can not be moved to RT2860_probe() even register_netdev()
is changed as register_netdevice().
Or in some PC, kernel will panic (Fedora 4) */
/* RT28xx_MBSS_Init(pAd, pAd->net_dev); os abl move to rt_main_dev.c*/
#endif /* MBSS_SUPPORT */
#ifdef WDS_SUPPORT
/* RT28xx_WDS_Init(pAd, pAd->net_dev);*/
#endif /* WDS_SUPPORT */
#ifdef APCLI_SUPPORT
/* RT28xx_ApCli_Init(pAd, pAd->net_dev);*/
#endif /* APCLI_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef UAPSD_SUPPORT
UAPSD_Init(pAd);
#endif /* UAPSD_SUPPORT */
/* assign function pointers*/
#ifdef MAT_SUPPORT
/* init function pointers, used in OS_ABL */
RTMP_MATOpsInit(pAd);
#endif /* MAT_SUPPORT */
#ifdef RTMP_RBUS_SUPPORT
if (pAd->infType == RTMP_DEV_INF_RBUS)
{
#ifdef VIDEO_TURBINE_SUPPORT
VideoTurbineDynamicTune(pAd);
#endif /* VIDEO_TURBINE_SUPPORT */
#ifdef RT3XXX_ANTENNA_DIVERSITY_SUPPORT
RT3XXX_AntDiversity_Init(pAd);
#endif /* RT3XXX_ANTENNA_DIVERSITY_SUPPORT */
}
#endif /* RTMP_RBUS_SUPPORT */
#ifdef P2P_SUPPORT
/* RTMP_P2P_Init(pAd, pAd->net_dev); */
#endif /* P2P_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MAT_SUPPORT
MATEngineInit(pAd);
#endif /* MAT_SUPPORT */
#ifdef CLIENT_WDS
CliWds_ProxyTabInit(pAd);
#endif /* CLIENT_WDS */
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
#ifdef DOT11Z_TDLS_SUPPORT
TDLS_Table_Init(pAd);
#endif /* DOT11Z_TDLS_SUPPORT */
#ifdef WPA_SUPPLICANT_SUPPORT
#ifndef NATIVE_WPA_SUPPLICANT_SUPPORT
/* send wireless event to wpa_supplicant for infroming interface up.*/
RtmpOSWrielessEventSend(pAd->net_dev, RT_WLAN_EVENT_CUSTOM, RT_INTERFACE_UP, NULL, NULL, 0);
#endif /* NATIVE_WPA_SUPPLICANT_SUPPORT */
#endif /* WPA_SUPPLICANT_SUPPORT */
}
#endif /* CONFIG_STA_SUPPORT */
/* auto-fall back settings */
RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, 0xedcba980); /* Fallback MCS8->MCS0 */
#ifdef DOT11N_SS3_SUPPORT
if (pAd->CommonCfg.TxStream >= 3)
{
RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_0, 0x12111008);
RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_1, 0x16151413);
}
#endif /* DOT11N_SS3_SUPPORT */
#ifdef STREAM_MODE_SUPPORT
RtmpStreamModeInit(pAd);
#endif /* STREAM_MODE_SUPPORT */
#if defined(RT2883) || defined(RT3883)
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
UINT8 BBPValue = 0;
BBP_IO_READ8_BY_REG_ID(pAd, BBP_R65, &BBPValue);
if (pAd->CommonCfg.FineAGC)
BBPValue |= 0x40; /* turn on fine AGC*/
else
BBPValue &= ~0x40; /* turn off fine AGC*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R65, BBPValue);
}
#endif /* defined(RT2883) || defined(RT3883) */
#ifdef DOT11_N_SUPPORT
#ifdef TXBF_SUPPORT
if (pAd->CommonCfg.ITxBfTimeout)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, 0x02);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 0);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, pAd->CommonCfg.ITxBfTimeout & 0xFF);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 1);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, (pAd->CommonCfg.ITxBfTimeout>>8) & 0xFF);
}
/*
========================================================================
Routine Description: Read RT30xx RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS RT30xxReadRFRegister(
IN PRTMP_ADAPTER pAd,
IN UCHAR regID,
IN PUCHAR pValue)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i=0, k=0;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxReadRFRegister. Not allow to read RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif // RTMP_MAC_PCI //
{
if (IS_RT3883(pAd))
{
ASSERT((regID <= 63)); // R0~R63
}
else
{
ASSERT((regID <= 31)); // R0~R31
}
for (i=0; i<MAX_BUSY_COUNT; i++)
{
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (rfcsr.field.RF_CSR_KICK == BUSY)
{
continue;
}
rfcsr.word = 0;
rfcsr.field.RF_CSR_WR = 0;
rfcsr.field.RF_CSR_KICK = 1;
rfcsr.field.TESTCSR_RFACC_REGNUM = regID;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
for (k=0; k<MAX_BUSY_COUNT; k++)
{
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (rfcsr.field.RF_CSR_KICK == IDLE)
break;
}
if ((rfcsr.field.RF_CSR_KICK == IDLE) &&
(rfcsr.field.TESTCSR_RFACC_REGNUM == regID))
{
*pValue = (UCHAR)(rfcsr.field.RF_CSR_DATA);
break;
}
}
if (rfcsr.field.RF_CSR_KICK == BUSY)
{
DBGPRINT_ERR(("RF read R%d=0x%X fail, i[%d], k[%d]\n", regID, rfcsr.word,i,k));
return STATUS_UNSUCCESSFUL;
}
}
return STATUS_SUCCESS;
}
/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
/* fill TxWI */
TxHTPhyMode.field.BW = pATEInfo->TxWI.BW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.ShortGI;
TxHTPhyMode.field.STBC = pATEInfo->TxWI.STBC;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.MCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.PHYMODE;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.FRAG, pATEInfo->TxWI.CFACK,
pATEInfo->TxWI.TS, pATEInfo->TxWI.AMPDU, pATEInfo->TxWI.ACK,
pATEInfo->TxWI.NSEQ, pATEInfo->TxWI.BAWinSize, 0,
pATEInfo->TxWI.MPDUtotalByteCount, pATEInfo->TxWI.PacketId, 0, 0,
pATEInfo->TxWI.txop/*IFS_HTTXOP*/, pATEInfo->TxWI.CFACK/*FALSE*/,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
/* Must copy rsv bits to actual TxWI */
pTxWI->rsv = pATEInfo->TxWI.rsv;
pTxWI->iTxBF = pATEInfo->TxWI.iTxBF;
pTxWI->Sounding = pATEInfo->TxWI.Sounding;
pTxWI->eTxBF = pATEInfo->TxWI.eTxBF;
pTxWI->Autofallback = pATEInfo->TxWI.Autofallback;
pTxWI->NDPSndBW = pATEInfo->TxWI.NDPSndBW;
pTxWI->NDPSndRate = pATEInfo->TxWI.NDPSndRate;
}
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (pATEInfo->bTxBF == 1)
{
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
pTxWI->rsv = 0;
pTxWI->iTxBF = pATEInfo->TxWI.iTxBF;
pTxWI->Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->eTxBF = pATEInfo->TxWI.eTxBF;
pTxWI->Autofallback = pATEInfo->TxWI.Autofallback;
pTxWI->NDPSndBW = pATEInfo->TxWI.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->NDPSndRate = 1;
else
pTxWI->NDPSndRate = 0;
}
}
#endif /* TXBF_SUPPORT */
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
#ifdef TXBF_SUPPORT
TemplateFrame[0] = 0x08; /* Data */
TemplateFrame[1] = 0x00;
if (pATEInfo->bTxBF && pATEInfo->txSoundingMode!=0)
{
/* QoS Data */
pATEInfo->HLen = 32;
TemplateFrame[0] = 0x88;
TemplateFrame[1] = 0x80;
switch (pATEInfo->txSoundingMode)
{
case 1:
/* Data Sounding */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x00;
break;
case 2:
case 3:
/* 2 or 3 Stream NDP */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x01; /* NDP Announce */
break;
default:
TemplateFrame[28] = TemplateFrame[29] = 0x0;
}
}
#endif /* TXBF_SUPPORT */
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, ETH_LENGTH_OF_ADDRESS);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
/* default payload is 0xA5 */
pDest[pos] = pATEInfo->Payload;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + LENGTH_802_11;
pTxD->LastSec0 = 0;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec1 = 1;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
/*
========================================================================
Routine Description:
Periodic evaluate antenna link status
Arguments:
pAd - Adapter pointer
Return Value:
None
========================================================================
*/
VOID APAsicEvaluateRxAnt(
IN PRTMP_ADAPTER pAd)
{
UCHAR BBPR3 = 0;
ULONG TxTotalCnt;
#ifdef RALINK_ATE
if (ATE_ON(pAd))
return;
#endif /* RALINK_ATE */
#ifdef CARRIER_DETECTION_SUPPORT
if(pAd->CommonCfg.CarrierDetect.CD_State == CD_SILENCE)
return;
#endif /* CARRIER_DETECTION_SUPPORT */
#ifdef TXBF_SUPPORT
/* TODO: we didn't do RxAnt evaluate for 3x3 chips */
if (IS_RT3883(pAd) || IS_RT2883(pAd))
return;
#endif /* TXBF_SUPPORT */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
BBPR3 &= (~0x18);
if((pAd->Antenna.field.RxPath == 3)
#ifdef DOT11_N_SUPPORT
#ifdef GREENAP_SUPPORT
&& (pAd->ApCfg.bGreenAPActive == FALSE)
#endif /* GREENAP_SUPPORT */
#endif /* DOT11_N_SUPPORT */
)
{
BBPR3 |= (0x10);
}
else if((pAd->Antenna.field.RxPath == 2)
#ifdef DOT11_N_SUPPORT
#ifdef GREENAP_SUPPORT
&& (pAd->ApCfg.bGreenAPActive == FALSE)
#endif /* GREENAP_SUPPORT */
#endif /* DOT11_N_SUPPORT */
)
{
BBPR3 |= (0x8);
}
else if(pAd->Antenna.field.RxPath == 1)
{
BBPR3 |= (0x0);
}
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
TxTotalCnt = pAd->RalinkCounters.OneSecTxNoRetryOkCount +
pAd->RalinkCounters.OneSecTxRetryOkCount +
pAd->RalinkCounters.OneSecTxFailCount;
if (TxTotalCnt > 50)
{
RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20);
pAd->Mlme.bLowThroughput = FALSE;
}
else
{
RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 300);
pAd->Mlme.bLowThroughput = TRUE;
}
}
VOID RT33xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
#ifdef DOT11N_SS3_SUPPORT
CHAR TxPwer3 = 0;
#endif /* DOT11N_SS3_SUPPORT */
#ifdef RT30xx
UCHAR Tx0FinePowerCtrl = 0, Tx1FinePowerCtrl = 0;
BBP_R109_STRUC BbpR109 = {{0}};
#endif /* RT30xx */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
#ifdef DOT11N_SS3_SUPPORT
if (IS_RT2883(pAd) || IS_RT3593(pAd) || IS_RT3883(pAd))
TxPwer3 = pAd->TxPower[index].Power3;
#endif /* DOT11N_SS3_SUPPORT */
#ifdef RT30xx /*RT33xx*/
if ((IS_RT3090A(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd)))/*&&*/
/*(pAd->infType == RTMP_DEV_INF_PCI || pAd->infType == RTMP_DEV_INF_PCIE))*/
{
Tx0FinePowerCtrl = pAd->TxPower[index].Tx0FinePowerCtrl;
Tx1FinePowerCtrl = pAd->TxPower[index].Tx1FinePowerCtrl;
}
#endif /* RT30xx */
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
#ifdef RT30xx
/* The RF programming sequence is difference between 3xxx and 2xxx*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
/* modify by WY for Read RF Reg. error */
UCHAR calRFValue;
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters*/
RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
/*
RT3370/RT3390 RF version is 0x3320 RF_R3 [7:4] is not reserved bits
RF_R3[6:4] (pa1_bc_cck) : PA1 Bias CCK
RF_R3[7] (pa2_cc_cck) : PA2 Cascode Bias CCK
*/
RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)(&RFValue));
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K & ~0xF0); /* <bit 3:0>:K<bit 3:0>*/
RT30xxWriteRFRegister(pAd, RF_R03, RFValue);
RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
/* Set Tx0 Power*/
RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
/* Set Tx1 Power*/
RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer2;
RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
#ifdef RT33xx
#endif /* RT33xx */
/* Tx/Rx Stream setting*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
/*if (IS_RT3090(pAd))*/
/* RFValue |= 0x01; Enable RF block.*/
RFValue &= 0xC3; /*clear bit[7~2]*/
if (pAd->Antenna.field.TxPath == 1)
RFValue |= 0x20;
else if (pAd->Antenna.field.TxPath == 2)
;
if (pAd->Antenna.field.RxPath == 1)
RFValue |= 0x10;
else if (pAd->Antenna.field.RxPath == 2)
;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
/* Set RF offset*/
RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
/* Set BW*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR24;
/*DISABLE_11N_CHECK(pAd);*/
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR24;
}
/*
RT3370/RT3390 RF version is 0x3320 RF_R24 [7:6] is not reserved bits
RF_R24[6] (BB_Rx1_out_en) : enable baseband output and ADC input
RF_R24[7] (BB_Tx1_out_en) : enable DAC output or baseband input
*/
RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R24, calRFValue);
/*
RT3370/RT3390 RF version is 0x3320 RF_R31 [7:6] is not reserved bits
RF_R31[4:0] (rx_agc_fc) : capacitor control in baseband filter
RF_R31[5] (rx_ h20M) : rx_ h20M: 0=10 MHz and 1=20MHz
RF_R31[7:6] (drv_bc_cck) : Driver Bias CCK
*/
/* Set BW*/
if (IS_RT3390(pAd)) /* RT3390 has different AGC for Tx and Rx*/
{
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR31;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR31;
}
}
RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:rx_h20M<bit 5> and <bit 4:0>:rx_agc_fc<bit 4:0> */
RT30xxWriteRFRegister(pAd, RF_R31, calRFValue);
/* Enable RF tuning*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue = RFValue | 0x1;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
/* latch channel for future usage.*/
pAd->LatchRfRegs.Channel = Channel;
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
break;
}
}
}
#endif /* RT30xx */
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* GPIO control*/
/* R66 should be set according to Channel and use 20MHz when scanning*/
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/* On 11A, We should delay and wait RF/BBP to be stable*/
/* and the appropriate time should be 1000 micro seconds */
/* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/
RTMPusecDelay(1000);
}
INT ATESetUpNDPAFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
TXINFO_STRUC *pTxInfo;
TXD_STRUC *pTxD;
#ifdef RT_BIG_ENDIAN
TXD_STRUC *pDestTxD;
UCHAR tx_hw_info[TXD_SIZE];
#endif /* RT_BIG_ENDIAN */
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
UCHAR *buf;
VHT_NDPA_FRAME *vht_ndpa;
SNDING_STA_INFO *sta_info;
RTMP_TX_RING *pTxRing = &pAd->TxRing[QID_AC_BE];
TXWI_STRUC *pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
UCHAR bw, sgi, stbc, mcs, phy_mode, frag, cfack, ts, ampdu, ack, nseq, bawinsize, pkt_id, txop;
USHORT byte_cnt;
bw = sgi = stbc = mcs = phy_mode = frag = cfack = ts =0;
ampdu = ack = nseq = bawinsize = pkt_id = txop = 0;
byte_cnt = 0;
#ifdef RLT_MAC
if (pAd->chipCap.hif_type == HIF_RLT) {
bw = pATEInfo->TxWI.TXWI_N.BW;
sgi = pATEInfo->TxWI.TXWI_N.ShortGI;
stbc = pATEInfo->TxWI.TXWI_N.STBC;
mcs = pATEInfo->TxWI.TXWI_N.MCS;
phy_mode = pATEInfo->TxWI.TXWI_N.PHYMODE;
frag = pATEInfo->TxWI.TXWI_N.FRAG;
cfack = pATEInfo->TxWI.TXWI_N.CFACK,
ts = pATEInfo->TxWI.TXWI_N.TS;
ampdu = pATEInfo->TxWI.TXWI_N.AMPDU;
ack = pATEInfo->TxWI.TXWI_N.ACK;
nseq = pATEInfo->TxWI.TXWI_N.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_N.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_N.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_N.TxPktId;
txop = pATEInfo->TxWI.TXWI_N.txop;
cfack = pATEInfo->TxWI.TXWI_N.CFACK;
}
#endif /* RLT_MAC */
#ifdef RTMP_MAC
if (pAd->chipCap.hif_type == HIF_RTMP) {
bw = pATEInfo->TxWI.TXWI_O.BW;
sgi = pATEInfo->TxWI.TXWI_O.ShortGI;
stbc = pATEInfo->TxWI.TXWI_O.STBC;
mcs = pATEInfo->TxWI.TXWI_O.MCS;
phy_mode = pATEInfo->TxWI.TXWI_O.PHYMODE;
frag = pATEInfo->TxWI.TXWI_O.FRAG;
cfack = pATEInfo->TxWI.TXWI_O.CFACK,
ts = pATEInfo->TxWI.TXWI_O.TS;
ampdu = pATEInfo->TxWI.TXWI_O.AMPDU;
ack = pATEInfo->TxWI.TXWI_O.ACK;
nseq = pATEInfo->TxWI.TXWI_O.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_O.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_O.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_O.PacketId;
txop = pATEInfo->TxWI.TXWI_O.txop;
cfack = pATEInfo->TxWI.TXWI_O.CFACK;
}
#endif /* RTMP_MAC */
/* fill TxWI */
TxHTPhyMode.field.BW = bw;
TxHTPhyMode.field.ShortGI = sgi;
TxHTPhyMode.field.STBC = stbc;
TxHTPhyMode.field.MCS = mcs;
TxHTPhyMode.field.MODE = phy_mode;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, frag, cfack,
ts, ampdu, ack,
nseq, bawinsize, 0,
byte_cnt, pkt_id, 0, 0,
txop, cfack,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
#ifdef RTMP_MAC
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
/* Must copy rsv bits to actual TxWI */
//pTxWI->TXWI_O.rsv = pATEInfo->TxWI.TXWI_O.rsv;
pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF;
pTxWI->TXWI_O.Sounding = pATEInfo->TxWI.TXWI_O.Sounding;
pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF;
pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback;
pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.NDPSndBW;
pTxWI->TXWI_O.NDPSndRate = pATEInfo->TxWI.TXWI_O.NDPSndRate;
}
#endif
#ifdef RLT_MAC
if (IS_MT76x2(pAd))
{
/* Must copy rsv bits to actual TxWI */
pTxWI->TXWI_N.Rsv4 = pATEInfo->TxWI.TXWI_N.Rsv4;
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.Sounding = pATEInfo->TxWI.TXWI_N.Sounding;
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
//pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.NDPSndBW;
pTxWI->TXWI_N.NDPSndRate = pATEInfo->TxWI.TXWI_N.NDPSndRate;
pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA;
}
#endif
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (pATEInfo->bTxBF == 1)
{
#ifdef RTMP_MAC
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
//pTxWI->TXWI_O.rsv = 0;
pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF;
pTxWI->TXWI_O.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF;
pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback;
pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->TXWI_O.NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->TXWI_O.NDPSndRate = 1;
else
pTxWI->TXWI_O.NDPSndRate = 0;
}
#endif
#ifdef RLT_MAC
if (IS_MT76x2(pAd))
{
pTxWI->TXWI_N.Rsv4 = 0;
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
//pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->TXWI_N.NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->TXWI_N.NDPSndRate = 1;
else
pTxWI->TXWI_N.NDPSndRate = 0;
pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA;
}
#endif
}
#endif /* TXBF_SUPPORT */
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
buf = (pDMAHeaderBufVA + TXWISize);
vht_ndpa = (VHT_NDPA_FRAME *)buf;
pATEInfo->HLen = sizeof(VHT_NDPA_FRAME);
vht_ndpa->fc.Type = FC_TYPE_CNTL;
vht_ndpa->fc.SubType = SUBTYPE_VHT_NDPA;
COPY_MAC_ADDR(vht_ndpa->ra, pATEInfo->Addr1);
COPY_MAC_ADDR(vht_ndpa->ta, pATEInfo->Addr3);
hex_dump("NDPA Frame",buf,pATEInfo->HLen);
/* Currnetly we only support 1 STA for a VHT DNPA */
sta_info = vht_ndpa->sta_info;
sta_info->aid12 = 1;
sta_info->fb_type = SNDING_FB_SU;
sta_info->nc_idx = 0;
vht_ndpa->token.token_num = 0;
vht_ndpa->duration = 100;
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
pDest[pos] = 0x00;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
pTxInfo = (TXINFO_STRUC *)(pTxRing->Cell[TxIdx].AllocVa + sizeof(TXD_STRUC));
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
NdisMoveMemory(&tx_hw_info[0], (UCHAR *)pDestTxD, TXD_SIZE);
pTxD = (TXD_STRUC *)&tx_hw_info[0];
pTxInfo = (TXINFO_STRUC *)(&tx_hw_info[0] + sizeof(TXD_STRUC));
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
TX_BLK txblk;
txblk.SrcBufLen = GET_OS_PKT_LEN(pPacket);
txblk.pSrcBufData = AllocVa;
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen /* LENGTH_802_11 */;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, &txblk, 0, 1, RTMP_PCI_DMA_TODEVICE);
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
TXINFO_STRUC *pTxInfo;
TXD_STRUC *pTxD;
#ifdef RT_BIG_ENDIAN
TXD_STRUC *pDestTxD;
UCHAR tx_hw_info[TXD_SIZE];
#endif /* RT_BIG_ENDIAN */
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
RTMP_TX_RING *pTxRing = &pAd->TxRing[QID_AC_BE];
TXWI_STRUC *pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
UCHAR bw, sgi, stbc, mcs, phy_mode, frag, cfack, ts, ampdu, ack, nseq, bawinsize, pkt_id, txop;
USHORT byte_cnt;
bw = sgi = stbc = mcs = phy_mode = frag = cfack = ts =0;
ampdu = ack = nseq = bawinsize = pkt_id = txop = 0;
byte_cnt = 0;
#ifdef RLT_MAC
if (pAd->chipCap.hif_type == HIF_RLT) {
bw = pATEInfo->TxWI.TXWI_N.BW;
sgi = pATEInfo->TxWI.TXWI_N.ShortGI;
stbc = pATEInfo->TxWI.TXWI_N.STBC;
mcs = pATEInfo->TxWI.TXWI_N.MCS;
phy_mode = pATEInfo->TxWI.TXWI_N.PHYMODE;
frag = pATEInfo->TxWI.TXWI_N.FRAG;
cfack = pATEInfo->TxWI.TXWI_N.CFACK,
ts = pATEInfo->TxWI.TXWI_N.TS;
ampdu = pATEInfo->TxWI.TXWI_N.AMPDU;
ack = pATEInfo->TxWI.TXWI_N.ACK;
nseq = pATEInfo->TxWI.TXWI_N.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_N.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_N.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_N.TxPktId;
txop = pATEInfo->TxWI.TXWI_N.txop;
cfack = pATEInfo->TxWI.TXWI_N.CFACK;
}
#endif /* RLT_MAC */
#ifdef RTMP_MAC
if (pAd->chipCap.hif_type == HIF_RTMP) {
bw = pATEInfo->TxWI.TXWI_O.BW;
sgi = pATEInfo->TxWI.TXWI_O.ShortGI;
stbc = pATEInfo->TxWI.TXWI_O.STBC;
mcs = pATEInfo->TxWI.TXWI_O.MCS;
phy_mode = pATEInfo->TxWI.TXWI_O.PHYMODE;
frag = pATEInfo->TxWI.TXWI_O.FRAG;
cfack = pATEInfo->TxWI.TXWI_O.CFACK,
ts = pATEInfo->TxWI.TXWI_O.TS;
ampdu = pATEInfo->TxWI.TXWI_O.AMPDU;
ack = pATEInfo->TxWI.TXWI_O.ACK;
nseq = pATEInfo->TxWI.TXWI_O.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_O.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_O.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_O.PacketId;
txop = pATEInfo->TxWI.TXWI_O.txop;
cfack = pATEInfo->TxWI.TXWI_O.CFACK;
}
#endif /* RTMP_MAC */
/* fill TxWI */
TxHTPhyMode.field.BW = bw;
TxHTPhyMode.field.ShortGI = sgi;
TxHTPhyMode.field.STBC = stbc;
TxHTPhyMode.field.MCS = mcs;
TxHTPhyMode.field.MODE = phy_mode;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, frag, cfack,
ts, ampdu, ack,
nseq, bawinsize, 0,
byte_cnt, pkt_id, 0, 0,
txop, cfack,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
#ifdef RTMP_MAC
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
/* Must copy rsv bits to actual TxWI */
//pTxWI->TXWI_O.Reserved = pATEInfo->TxWI.TXWI_O.Reserved;
pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF;
pTxWI->TXWI_O.Sounding = pATEInfo->TxWI.TXWI_O.Sounding;
pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF;
pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback;
pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.NDPSndBW;
pTxWI->TXWI_O.NDPSndRate = pATEInfo->TxWI.TXWI_O.NDPSndRate;
}
#endif
#ifdef RLT_MAC
if (IS_MT76x2(pAd))
{
/* Must copy rsv bits to actual TxWI */
pTxWI->TXWI_N.Rsv4 = pATEInfo->TxWI.TXWI_N.Rsv4;
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.Sounding = pATEInfo->TxWI.TXWI_N.Sounding;
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
//pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.NDPSndBW;
pTxWI->TXWI_N.NDPSndRate = pATEInfo->TxWI.TXWI_N.NDPSndRate;
pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA;
}
#endif
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (pATEInfo->bTxBF == 1)
{
#ifdef RTMP_MAC
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
//pTxWI->TXWI_O.Reserved = 0;
pTxWI->TXWI_O.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
if(pATEInfo->txSoundingMode)
{
pTxWI->TXWI_O.iTxBF = FALSE;
pTxWI->TXWI_O.eTxBF = FALSE;
}
else
{
pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF;
pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF;
}
pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback;
pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->TXWI_O.NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->TXWI_O.NDPSndRate = 1;
else
pTxWI->TXWI_O.NDPSndRate = 0;
}
#endif
#ifdef RLT_MAC
if (IS_MT76x2(pAd))
{
pTxWI->TXWI_N.Rsv4 = 0;
pTxWI->TXWI_N.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
if(pATEInfo->txSoundingMode)
{
pTxWI->TXWI_N.iTxBF = FALSE;
pTxWI->TXWI_N.eTxBF = FALSE;
}
else
{
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
}
//pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->TXWI_N.NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->TXWI_N.NDPSndRate = 1;
else
pTxWI->TXWI_N.NDPSndRate = 0;
pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA;
}
#endif
}
#endif /* TXBF_SUPPORT */
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
#ifdef TXBF_SUPPORT
TemplateFrame[0] = 0x08; /* Data */
TemplateFrame[1] = 0x00;
if (pATEInfo->bTxBF && pATEInfo->txSoundingMode!=0)
{
/* QoS Data */
//pATEInfo->HLen = 32;
pATEInfo->HLen = 30;
TemplateFrame[0] = 0x88;
TemplateFrame[1] = 0x80;
switch (pATEInfo->txSoundingMode)
{
case 1:
/* Data Sounding */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x00;
break;
case 2:
case 3:
/* 2 or 3 Stream NDP */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x01; /* NDP Announce */
break;
default:
TemplateFrame[28] = TemplateFrame[29] = 0x0;
}
}
#endif /* TXBF_SUPPORT */
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, MAC_ADDR_LEN);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, MAC_ADDR_LEN);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, MAC_ADDR_LEN);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
if ( pATEInfo->bFixedPayload )
{
pDest[pos] = pATEInfo->Payload;
// pDest[pos] = 0xA5;
}
else
{
pDest[pos] = RandomByte(pAd);
}
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
pTxInfo = (TXINFO_STRUC *)(pTxRing->Cell[TxIdx].AllocVa + sizeof(TXD_STRUC));
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
NdisMoveMemory(&tx_hw_info[0], (UCHAR *)pDestTxD, TXD_SIZE);
pTxD = (TXD_STRUC *)&tx_hw_info[0];
pTxInfo = (TXINFO_STRUC *)(&tx_hw_info[0] + sizeof(TXD_STRUC));
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
TX_BLK txblk;
txblk.SrcBufLen = GET_OS_PKT_LEN(pPacket);
txblk.pSrcBufData = AllocVa;
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen /* LENGTH_802_11 */;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, &txblk, 0, 1, RTMP_PCI_DMA_TODEVICE);
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
//#endif
return 0;
}
