NTSTATUS RTMP_BBP_IO_WRITE8_BY_REG_ID(
RTMP_ADAPTER *pAd,
UINT32 Offset,
UINT8 Value)
{
#ifdef RT65xx
if (IS_RT65XX(pAd))
return STATUS_UNSUCCESSFUL;
#endif /* RT65xx */
#ifdef RTMP_MAC_PCI
/*
This marco used for the BBP write operation which need via MCU.
But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
will use this function too and didn't access the bbp register via the MCU.
*/
if ((pAd)->bPCIclkOff == FALSE)
{
if ((pAd)->infType == RTMP_DEV_INF_RBUS)
RTMP_BBP_IO_WRITE8(pAd, Offset, Value, FALSE);
else
if(IS_SUPPORT_PCIE_PS_L3(pAd))
RTMP_PCIE_PS_L3_BBP_IO_WRITE8(pAd, Offset, Value, TRUE);
else
RTMP_BBP_IO_WRITE8(pAd, Offset, Value, TRUE);
}
return STATUS_SUCCESS;
#endif /* RTMP_MAC_PCI */
}
CHAR ConvertToRssi(RTMP_ADAPTER *pAd, CHAR Rssi, UCHAR rssi_idx)
{
UCHAR RssiOffset, LNAGain;
/* Rssi equals to zero or rssi_idx larger than 3 should be an invalid value*/
if (Rssi == 0 || rssi_idx >= 3)
return -99;
LNAGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel > 14)
RssiOffset = pAd->ARssiOffset[rssi_idx];
else
RssiOffset = pAd->BGRssiOffset[rssi_idx];
#ifdef RT65xx
/*
Recommended by CSD team:
2.4G : RSSI_report = RSSI_bpp + EEPROM_0x46[15:8 or 7:0] - EEPROM_0x44[7:0]
5G : RSSI_report = RSSI_bbp + EEPROM_0x4A[15:8 or 7:0] - EEPROM_0x44 or 0x48 or 0x4c[15:8]
*/
if (IS_RT65XX(pAd))
return (Rssi + RssiOffset - LNAGain);
else
#endif /* RT65xx */
return (-12 - RssiOffset - LNAGain - Rssi);
}
static inline BOOLEAN rf_csr_poll_idle(RTMP_ADAPTER *pAd, UINT32 *rfcsr)
{
RF_CSR_CFG_STRUC *csr_val;
BOOLEAN idle = BUSY;
INT i = 0;
do
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
break;
RTMP_IO_READ32(pAd, RF_CSR_CFG, rfcsr);
csr_val = (RF_CSR_CFG_STRUC *)rfcsr;
#ifdef RT65xx
if (IS_RT65XX(pAd))
idle = csr_val->bank_65xx.RF_CSR_KICK;
else
#endif /* RT65xx */
idle = csr_val->non_bank.RF_CSR_KICK;
if (idle == IDLE)
break;
i++;
} while (i < MAX_BUSY_COUNT);
if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed(cnt=%d)!\n", i));
}
return idle;
}
NDIS_STATUS rlt_rf_write(
IN PRTMP_ADAPTER pAd,
IN UCHAR bank,
IN UCHAR regID,
IN UCHAR value)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
NDIS_STATUS ret;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("rlt_rf_write. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
#ifdef RLT_MAC
// TODO: shiang-usw, why we need to check this for MT7601?? Get these code from MT7601!
if (pAd->chipCap.hif_type == HIF_RLT) {
if (pAd->WlanFunCtrl.field.WLAN_EN == 0)
{
DBGPRINT_ERR(("rlt_rf_write. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
}
#endif /* RLT_MAC */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
ret = STATUS_UNSUCCESSFUL;
if (rf_csr_poll_idle(pAd, &rfcsr.word) != IDLE)
goto done;
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
rfcsr.bank_65xx.RF_CSR_WR = 1;
rfcsr.bank_65xx.RF_CSR_KICK = 1;
rfcsr.bank_65xx.RF_CSR_REG_BANK = bank;
rfcsr.bank_65xx.RF_CSR_REG_ID = regID;
rfcsr.bank_65xx.RF_CSR_DATA = value;
}
else
#endif /* RT65xx */
{
DBGPRINT_ERR(("%s():RF write with wrong handler!\n", __FUNCTION__));
goto done;
}
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
ret = NDIS_STATUS_SUCCESS;
done:
return ret;
}
/*
========================================================================
Routine Description:
Periodic evaluate antenna link status
Arguments:
pAd - Adapter pointer
Return Value:
None
========================================================================
*/
VOID APAsicEvaluateRxAnt(
IN PRTMP_ADAPTER pAd)
{
ULONG TxTotalCnt;
#ifdef RALINK_ATE
if (ATE_ON(pAd))
return;
#endif /* RALINK_ATE */
#ifdef CARRIER_DETECTION_SUPPORT
if(pAd->CommonCfg.CarrierDetect.CD_State == CD_SILENCE)
return;
#endif /* CARRIER_DETECTION_SUPPORT */
#ifdef RT8592
// TODO: shiang-6590, for 8592, this EvaaluateRxAnt still need??
if (IS_RT8592(pAd))
return;
#endif /* RT8592 */
#ifdef RT65xx
if (IS_RT65XX(pAd))
return;
#endif /* RT76x0 */
#ifdef TXBF_SUPPORT
/* TODO: we didn't do RxAnt evaluate for 3x3 chips */
if (IS_RT3883(pAd) || IS_RT2883(pAd))
return;
#endif /* TXBF_SUPPORT */
#ifdef DOT11_N_SUPPORT
#ifdef GREENAP_SUPPORT
if (pAd->ApCfg.bGreenAPActive == TRUE)
bbp_set_rxpath(pAd, 1);
else
#endif /* GREENAP_SUPPORT */
#endif /* DOT11_N_SUPPORT */
bbp_set_rxpath(pAd, pAd->Antenna.field.RxPath);
TxTotalCnt = pAd->RalinkCounters.OneSecTxNoRetryOkCount +
pAd->RalinkCounters.OneSecTxRetryOkCount +
pAd->RalinkCounters.OneSecTxFailCount;
if (TxTotalCnt > 50)
{
RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20);
pAd->Mlme.bLowThroughput = FALSE;
}
else
{
RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 300);
pAd->Mlme.bLowThroughput = TRUE;
}
}
static BOOLEAN AsicGetMacVersion(RTMP_ADAPTER *pAd)
{
UINT32 reg = MAC_CSR0;
#ifdef RT65xx
if (IS_RT65XX(pAd))
RTMP_IO_READ32(pAd, ASIC_VERSION, &pAd->ChipID);
#endif /* RT65xx */
if (WaitForAsicReady(pAd) == TRUE) {
RTMP_IO_READ32(pAd, reg, &pAd->MACVersion);
DBGPRINT(RT_DEBUG_OFF, ("MACVersion[Ver:Rev]=0x%08x : 0x%08x\n",
pAd->MACVersion, pAd->ChipID));
return TRUE;
} else {
DBGPRINT(RT_DEBUG_ERROR, ("%s() failed!\n", __FUNCTION__));
return FALSE;
}
}
/*
========================================================================
Routine Description: Read RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS rlt_rf_read(
IN RTMP_ADAPTER *pAd,
IN UCHAR bank,
IN UCHAR regID,
IN UCHAR *pValue)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i=0, k=0;
BOOLEAN rf_status;
NDIS_STATUS ret = STATUS_UNSUCCESSFUL;
#ifdef MT76x0
if (IS_MT7610U(pAd)) {
BANK_RF_REG_PAIR reg;
reg.Bank = bank;
reg.Register = regID;
RF_RANDOM_READ(pAd, ®, 1);
*pValue = reg.Value;
return NDIS_STATUS_SUCCESS;
}
#endif /* MT76x0 */
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxReadRFRegister. Not allow to read RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
#ifdef RTMP_MAC_USB
if (IS_USB_INF(pAd)) {
RTMP_SEM_EVENT_WAIT(&pAd->reg_atomic, i);
if (i != 0) {
DBGPRINT(RT_DEBUG_ERROR, ("reg_atomic get failed(ret=%d)\n", i));
return STATUS_UNSUCCESSFUL;
}
}
#endif /* RTMP_MAC_USB */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
rfcsr.word = 0;
for (i=0; i<MAX_BUSY_COUNT; i++)
{
if(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
goto done;
rf_status = rf_csr_poll_idle(pAd, &rfcsr.word);
if ( rf_status == BUSY)
break;
rfcsr.word = 0;
#ifdef RT6352
if (IS_RT6352(pAd))
{
rfcsr.bank_6352.RF_CSR_WR = 0;
rfcsr.bank_6352.RF_CSR_KICK = 1;
rfcsr.bank_6352.TESTCSR_RFACC_REGNUM = (regID | (bank << 6));
}
else
#endif /* RT6352 */
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
rfcsr.bank_65xx.RF_CSR_WR = 0;
rfcsr.bank_65xx.RF_CSR_KICK = 1;
rfcsr.bank_65xx.RF_CSR_REG_ID = regID;
rfcsr.bank_65xx.RF_CSR_REG_BANK = bank;
}
else
#endif /* RT65xx */
{
DBGPRINT_ERR(("RF[%d] read function for non-supported chip[0x%x]\n", regID, pAd->MACVersion));
break;
}
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
rf_status = rf_csr_poll_idle(pAd, &rfcsr.word);
if (rf_status == IDLE)
{
#ifdef RT6352
if (IS_RT6352(pAd) && ((rfcsr.bank_6352.TESTCSR_RFACC_REGNUM & 0x3F) == regID))
{
*pValue = (UCHAR)(rfcsr.bank_6352.RF_CSR_DATA);
break;
}
#endif /* RT6352 */
#ifdef RT65xx
if (IS_RT65XX(pAd) && (rfcsr.bank_65xx.RF_CSR_REG_ID == regID) &&
(rfcsr.bank_65xx.RF_CSR_REG_BANK == bank))
{
*pValue = (UCHAR)(rfcsr.bank_65xx.RF_CSR_DATA);
break;
}
#endif /* RT65xx */
}
}
if (rf_status == BUSY)
{
DBGPRINT_ERR(("RF read R%d=0x%X fail, i[%d], k[%d]\n", regID, rfcsr.word,i,k));
goto done;
}
ret = STATUS_SUCCESS;
#if 0
if (bank >= RF_BANK4)
{
printk("TESTCSR_RFACC_REGNUM = %x, RF_CSR_DATA = %x !!!\n", rfcsr.field.TESTCSR_RFACC_REGNUM, rfcsr.field.RF_CSR_DATA);
}
#endif
done:
#ifdef RTMP_MAC_USB
if (IS_USB_INF(pAd)) {
RTMP_SEM_EVENT_UP(&pAd->reg_atomic);
}
#endif /* RTMP_MAC_USB */
return ret;
}
INT rtmp_mac_fifo_stat_update(RTMP_ADAPTER *pAd)
{
TX_STA_FIFO_STRUC StaFifo;
TX_STA_FIFO_EXT_STRUC StaFifoExt;
MAC_TABLE_ENTRY *pEntry = NULL;
UINT32 i = 0;
UCHAR pid = 0, wcid = 0;
INT32 reTry;
UCHAR succMCS;
do
{
#ifdef FIFO_EXT_SUPPORT
if (IS_RT65XX(pAd)) {
RTMP_IO_READ32(pAd, TX_STA_FIFO_EXT, &StaFifoExt.word);
}
#endif /* FIFO_EXT_SUPPORT */
RTMP_IO_READ32(pAd, TX_STA_FIFO, &StaFifo.word);
if (StaFifo.field.bValid == 0)
break;
wcid = (UCHAR)StaFifo.field.wcid;
#ifdef DBG_CTRL_SUPPORT
#ifdef INCLUDE_DEBUG_QUEUE
if (pAd->CommonCfg.DebugFlags & DBF_DBQ_TXFIFO) {
dbQueueEnqueue(0x73, (UCHAR *)(&StaFifo.word));
}
#endif /* INCLUDE_DEBUG_QUEUE */
#endif /* DBG_CTRL_SUPPORT */
/* ignore NoACK and MGMT frame use 0xFF as WCID */
if ((StaFifo.field.TxAckRequired == 0) || (wcid >= MAX_LEN_OF_MAC_TABLE))
{
i++;
continue;
}
/* PID store Tx MCS Rate */
#ifdef FIFO_EXT_SUPPORT
if (IS_RT65XX(pAd))
pid = (UCHAR)StaFifoExt.field.pkt_id_65xx;
else
#endif /* FIFO_EXT_SUPPORT */
pid = (UCHAR)StaFifo.field.PidType;
pEntry = &pAd->MacTab.Content[wcid];
if (pEntry & pAd->MacTab.tr_entry[wcid].PsDeQWaitCnt)
pAd->MacTab.tr_entry[wcid].PsDeQWaitCnt = 0;
pEntry->DebugFIFOCount++;
#ifdef DOT11_N_SUPPORT
#endif /* DOT11_N_SUPPORT */
#ifdef UAPSD_SUPPORT
UAPSD_SP_AUE_Handle(pAd, pEntry, StaFifo.field.TxSuccess);
#endif /* UAPSD_SUPPORT */
if (!StaFifo.field.TxSuccess)
{
pEntry->FIFOCount++;
pEntry->OneSecTxFailCount++;
if (pEntry->FIFOCount >= 1)
{
DBGPRINT(RT_DEBUG_TRACE, ("#"));
#ifdef DOT11_N_SUPPORT
pEntry->NoBADataCountDown = 64;
#endif /* DOT11_N_SUPPORT */
/* Update the continuous transmission counter.*/
pEntry->ContinueTxFailCnt++;
// TODO: shiang-usw, remove upper setting because we need to mirgate to tr_entry!
pAd->MacTab.tr_entry[pEntry->wcid].ContinueTxFailCnt++;
if(pEntry->PsMode == PWR_ACTIVE)
{
#ifdef DOT11_N_SUPPORT
int tid;
for (tid=0; tid<NUM_OF_TID; tid++)
BAOriSessionTearDown(pAd, pEntry->wcid, tid, FALSE, FALSE);
#endif /* DOT11_N_SUPPORT */
#ifdef WDS_SUPPORT
/* fix WDS Jam issue*/
if(IS_ENTRY_WDS(pEntry)
&& (pEntry->LockEntryTx == FALSE)
&& (pEntry->ContinueTxFailCnt >= pAd->ApCfg.EntryLifeCheck))
{
DBGPRINT(RT_DEBUG_TRACE, ("Entry %02x:%02x:%02x:%02x:%02x:%02x Blocked!! (Fail Cnt = %d)\n",
PRINT_MAC(pEntry->Addr), pEntry->ContinueTxFailCnt ));
pEntry->LockEntryTx = TRUE;
// TODO: shiang-usw, remove upper setting because we need to mirgate to tr_entry!
pAd->MacTab.tr_entry[pEntry->wcid].LockEntryTx = TRUE;
}
#endif /* WDS_SUPPORT */
}
}
#ifdef CONFIG_AP_SUPPORT
#ifdef RTMP_MAC_PCI
/* if Tx fail >= 20, then clear TXWI ack in Tx Ring*/
if (pEntry->ContinueTxFailCnt >= pAd->ApCfg.EntryLifeCheck)
ClearTxRingClientAck(pAd, pEntry);
#endif /* RTMP_MAC_PCI */
#endif /* CONFIG_AP_SUPPORT */
}
else
{
#ifdef DOT11_N_SUPPORT
if ((pEntry->PsMode != PWR_SAVE) && (pEntry->NoBADataCountDown > 0))
{
pEntry->NoBADataCountDown--;
if (pEntry->NoBADataCountDown==0)
{
DBGPRINT(RT_DEBUG_TRACE, ("@\n"));
}
}
#endif /* DOT11_N_SUPPORT */
pEntry->FIFOCount = 0;
pEntry->OneSecTxNoRetryOkCount++;
/* update NoDataIdleCount when sucessful send packet to STA.*/
pEntry->NoDataIdleCount = 0;
pEntry->ContinueTxFailCnt = 0;
#ifdef WDS_SUPPORT
pEntry->LockEntryTx = FALSE;
#endif /* WDS_SUPPORT */
// TODO: shiang-usw, remove upper setting because we need to mirgate to tr_entry!
pAd->MacTab.tr_entry[pEntry->wcid].NoDataIdleCount = 0;
pAd->MacTab.tr_entry[pEntry->wcid].ContinueTxFailCnt = 0;
pAd->MacTab.tr_entry[pEntry->wcid].LockEntryTx = FALSE;
}
succMCS = StaFifo.field.SuccessRate & 0x7F;
#ifdef DOT11N_SS3_SUPPORT
if (pEntry->HTCapability.MCSSet[2] == 0xff)
{
if (succMCS > pid)
pid = pid + 16;
}
#endif /* DOT11N_SS3_SUPPORT */
if (StaFifo.field.TxSuccess)
{
pEntry->TXMCSExpected[pid]++;
if (pid == succMCS)
pEntry->TXMCSSuccessful[pid]++;
else
pEntry->TXMCSAutoFallBack[pid][succMCS]++;
}
else
{
pEntry->TXMCSFailed[pid]++;
}
#ifdef DOT11N_SS3_SUPPORT
if (pid >= 16 && succMCS <= 8)
succMCS += (2 - (succMCS >> 3)) * 7;
#endif /* DOT11N_SS3_SUPPORT */
reTry = pid - succMCS;
if (reTry > 0)
{
/* MCS8 falls back to 0 */
if (pid>=8 && succMCS==0)
reTry -= 7;
else if ((pid >= 12) && succMCS <=7)
reTry -= 4;
pEntry->OneSecTxRetryOkCount += reTry;
}
i++; /* ASIC store 16 stack*/
} while ( i < (TX_RING_SIZE<<1) );
}
VOID RTMP_BBP_IO_READ8(
PRTMP_ADAPTER pAd,
UCHAR bbp_id,
UINT8 *pValue,
BOOLEAN bViaMCU)
{
BBP_CSR_CFG_STRUC BbpCsr;
int _busyCnt, _secCnt, _regID;
ULONG __IrqFlags = 0;
#ifdef RT65xx
if (IS_RT65XX(pAd))
return;
#endif /* RT65xx */
if ((bViaMCU) == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_LOCK(pAd, __IrqFlags);
_regID = ((bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG);
for (_busyCnt=0; _busyCnt<MAX_BUSY_COUNT; _busyCnt++)
{
RTMP_IO_READ32(pAd, _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == BUSY)
continue;
BbpCsr.word = 0;
BbpCsr.field.fRead = 1;
BbpCsr.field.BBP_RW_MODE = 1;
BbpCsr.field.Busy = 1;
BbpCsr.field.RegNum = bbp_id;
RTMP_IO_WRITE32(pAd, _regID, BbpCsr.word);
if ((bViaMCU) == TRUE)
{
AsicSendCommandToMcuBBP(pAd, 0x80, 0xff, 0x0, 0x0, FALSE);
/*RtmpusecDelay(1000);*/
}
for (_secCnt=0; _secCnt<MAX_BUSY_COUNT; _secCnt++)
{
RTMP_IO_READ32(pAd, _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == IDLE)
break;
}
if ((BbpCsr.field.Busy == IDLE) && (BbpCsr.field.RegNum == bbp_id))
{
*pValue = (UCHAR)BbpCsr.field.Value;
break;
}
}
if (BbpCsr.field.Busy == BUSY)
{
DBGPRINT_ERR(("BBP(viaMCU=%d) read R%d fail\n", bViaMCU, bbp_id));
*pValue = pAd->BbpWriteLatch[bbp_id];
if (bViaMCU == TRUE)
{
RTMP_IO_READ32(pAd, _regID, &BbpCsr.word);
BbpCsr.field.Busy = 0;
RTMP_IO_WRITE32(pAd, _regID, BbpCsr.word);
}
}
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(pAd, __IrqFlags);
}
VOID RTMP_BBP_IO_WRITE8(
RTMP_ADAPTER *pAd,
UCHAR bbp_id,
UINT8 Value,
BOOLEAN bViaMCU)
{
BBP_CSR_CFG_STRUC BbpCsr;
int _busyCnt=0, _regID;
BOOLEAN brc;
ULONG __IrqFlags = 0;
#ifdef RT65xx
if (IS_RT65XX(pAd))
return;
#endif /* RT65xx */
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_LOCK(pAd, __IrqFlags);
_regID = (bViaMCU == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG);
for (_busyCnt=1; _busyCnt<MAX_BUSY_COUNT; _busyCnt++)
{
RTMP_IO_READ32((pAd), _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == BUSY)
{
if ( (bViaMCU == TRUE) && ((_busyCnt % 20) == 0))
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
continue;
}
BbpCsr.word = 0;
BbpCsr.field.fRead = 0;
BbpCsr.field.BBP_RW_MODE = 1;
BbpCsr.field.Busy = 1;
BbpCsr.field.Value = Value;
BbpCsr.field.RegNum = bbp_id;
RTMP_IO_WRITE32((pAd), _regID, BbpCsr.word);
if (bViaMCU == TRUE)
{
brc = AsicSendCommandToMcuBBP(pAd, 0x80, 0xff, 0x0, 0x0, FALSE);
if (pAd->OpMode == OPMODE_AP)
RtmpusecDelay(1000);
if (brc == FALSE)
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
pAd->BbpWriteLatch[bbp_id] = Value;
break;
}
if (_busyCnt == MAX_BUSY_COUNT)
{
DBGPRINT_ERR(("BBP write R%d fail\n", bbp_id));
if(bViaMCU == TRUE)
{
RTMP_IO_READ32(pAd, H2M_BBP_AGENT, &BbpCsr.word);
BbpCsr.field.Busy = 0;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(pAd, __IrqFlags);
}
/*
========================================================================
Routine Description:
Calculates the duration which is required to transmit out frames
with given size and specified rate.
Arguments:
pTxWI Pointer to head of each MPDU to HW.
Ack Setting for Ack requirement bit
Fragment Setting for Fragment bit
RetryMode Setting for retry mode
Ifs Setting for IFS gap
Rate Setting for transmit rate
Service Setting for service
Length Frame length
TxPreamble Short or Long preamble when using CCK rates
QueIdx - 0-3, according to 802.11e/d4.4 June/2003
Return Value:
None
See also : BASmartHardTransmit() !!!
========================================================================
*/
VOID RTMPWriteTxWI(
IN RTMP_ADAPTER *pAd,
IN TXWI_STRUC *pOutTxWI,
IN BOOLEAN FRAG,
IN BOOLEAN CFACK,
IN BOOLEAN InsTimestamp,
IN BOOLEAN AMPDU,
IN BOOLEAN Ack,
IN BOOLEAN NSeq, /* HW new a sequence.*/
IN UCHAR BASize,
IN UCHAR WCID,
IN ULONG Length,
IN UCHAR PID,
IN UCHAR TID,
IN UCHAR TxRate,
IN UCHAR Txopmode,
IN BOOLEAN CfAck,
IN HTTRANSMIT_SETTING *pTransmit)
{
PMAC_TABLE_ENTRY pMac = NULL;
TXWI_STRUC TxWI, *pTxWI;
UINT8 TXWISize = pAd->chipCap.TXWISize;
if (WCID < MAX_LEN_OF_MAC_TABLE)
pMac = &pAd->MacTab.Content[WCID];
/*
Always use Long preamble before verifiation short preamble functionality works well.
Todo: remove the following line if short preamble functionality works
*/
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
NdisZeroMemory(&TxWI, TXWISize);
pTxWI = &TxWI;
pTxWI->TxWIFRAG= FRAG;
pTxWI->TxWICFACK = CFACK;
pTxWI->TxWITS= InsTimestamp;
pTxWI->TxWIAMPDU = AMPDU;
pTxWI->TxWIACK = Ack;
pTxWI->TxWITXOP= Txopmode;
pTxWI->TxWINSEQ = NSeq;
/* John tune the performace with Intel Client in 20 MHz performance*/
#ifdef DOT11_N_SUPPORT
BASize = pAd->CommonCfg.TxBASize;
#ifdef RT65xx
if (IS_RT65XX(pAd))
{
if (BASize > 31)
BASize =31;
}
else
#endif /* RT65xx */
#ifdef MT7601
if (IS_MT7601(pAd))
{
if (BASize > 15)
BASize =15;
}
else
#endif /* MT7601 */
if (pAd->MACVersion == 0x28720200)
{
if (BASize > 13)
BASize =13;
}
else
{
if( BASize >7 )
BASize =7;
}
pTxWI->TxWIBAWinSize = BASize;
pTxWI->TxWIShortGI = pTransmit->field.ShortGI;
pTxWI->TxWISTBC = pTransmit->field.STBC;
#ifdef TXBF_SUPPORT
if (pMac && pAd->chipCap.FlgHwTxBfCap)
{
if (pMac->TxSndgType == SNDG_TYPE_NDP || pMac->TxSndgType == SNDG_TYPE_SOUNDING || pTxWI->eTxBF)
pTxWI->TxWISTBC = 0;
}
#endif /* TXBF_SUPPORT */
#endif /* DOT11_N_SUPPORT */
pTxWI->TxWIWirelessCliID = WCID;
pTxWI->TxWIMPDUByteCnt = Length;
#ifdef RLT_MAC
pTxWI->TxWIPacketId = PID;
#endif /* RLT_MAC */
/* If CCK or OFDM, BW must be 20*/
pTxWI->TxWIBW = (pTransmit->field.MODE <= MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
#ifdef DOT11_N_SUPPORT
#ifdef DOT11N_DRAFT3
if (pTxWI->TxWIBW)
pTxWI->TxWIBW = (pAd->CommonCfg.AddHTInfo.AddHtInfo.RecomWidth == 0) ? (BW_20) : (pTransmit->field.BW);
#endif /* DOT11N_DRAFT3 */
#endif /* DOT11_N_SUPPORT */
pTxWI->TxWIMCS = pTransmit->field.MCS;
pTxWI->TxWIPHYMODE = pTransmit->field.MODE;
pTxWI->TxWICFACK = CfAck;
#ifdef DOT11_N_SUPPORT
if (pMac)
{
if (pAd->CommonCfg.bMIMOPSEnable)
{
if ((pMac->MmpsMode == MMPS_DYNAMIC) && (pTransmit->field.MCS > 7))
{
/* Dynamic MIMO Power Save Mode*/
pTxWI->TxWIMIMOps = 1;
}
else if (pMac->MmpsMode == MMPS_STATIC)
{
/* Static MIMO Power Save Mode*/
if (pTransmit->field.MODE >= MODE_HTMIX && pTransmit->field.MCS > 7)
{
pTxWI->TxWIMCS = 7;
pTxWI->TxWIMIMOps = 0;
}
}
}
/*pTxWI->TxWIMIMOps = (pMac->PsMode == PWR_MMPS)? 1:0;*/
{
pTxWI->TxWIMpduDensity = pMac->MpduDensity;
}
}
#endif /* DOT11_N_SUPPORT */
#ifdef RLT_MAC
pTxWI->TxWIPacketId = pTxWI->TxWIMCS;
#endif /* RLT_MAC */
NdisMoveMemory(pOutTxWI, &TxWI, TXWISize);
//+++Add by shiang for debug
if (0){
hex_dump("TxWI", (UCHAR *)pOutTxWI, TXWISize);
}
//---Add by shiang for debug
}
/*
========================================================================
Routine Description:
Initialize chip related information.
Arguments:
pCB - WLAN control block pointer
Return Value:
None
Note:
========================================================================
*/
VOID RtmpChipOpsHook(VOID *pCB)
{
RTMP_ADAPTER *pAd = (RTMP_ADAPTER *)pCB;
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
RTMP_CHIP_CAP *pChipCap = &pAd->chipCap;
UINT32 MacValue;
/* sanity check */
WaitForAsicReady(pAd);
RTMP_IO_READ32(pAd, MAC_CSR0, &MacValue);
pAd->MACVersion = MacValue;
/* default init */
RTMP_DRS_ALG_INIT(pAd, RATE_ALG_LEGACY);
#ifdef RT3290
if (IS_RT3290(pAd))
{
RT3290_Init(pAd);
goto done;
}
#endif /* RT290 */
#ifdef RT8592
if (IS_RT8592(pAd)) {
RT85592_Init(pAd);
goto done;
}
#endif /* RT8592 */
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
RT6590_Init(pAd);
goto done;
}
#endif /* RT65xx */
#ifdef MT7601
if (IS_MT7601(pAd)) {
MT7601_Init(pAd);
goto done;
}
#endif /* MT7601 */
/* init default value whatever chipsets */
/* default pChipOps content will be 0x00 */
pChipCap->bbpRegTbSize = 0;
pChipCap->MaxNumOfRfId = 31;
pChipCap->MaxNumOfBbpId = 136;
pChipCap->SnrFormula = SNR_FORMULA1;
pChipCap->RfReg17WtMethod = RF_REG_WT_METHOD_NONE;
pChipCap->TXWISize = 16;
pChipCap->RXWISize = 16;
#if defined(RTMP_INTERNAL_TX_ALC) || defined(RTMP_TEMPERATURE_COMPENSATION)
pChipCap->TxPowerTuningTable_2G = TxPowerTuningTableOrg;
#ifdef A_BAND_SUPPORT
pChipCap->TxPowerTuningTable_5G = TxPowerTuningTableOrg;
#endif /* A_BAND_SUPPORT */
#endif /* defined(RTMP_INTERNAL_TX_ALC) || defined(RTMP_TEMPERATURE_COMPENSATION) */
pChipOps->AsicMacInit = NULL;
pChipOps->AsicBbpInit = NULL;
pChipOps->AsicRfInit = NULL;
#ifdef RTMP_EFUSE_SUPPORT
pChipCap->EFUSE_USAGE_MAP_START = 0x2d0;
pChipCap->EFUSE_USAGE_MAP_END = 0x2fc;
pChipCap->EFUSE_USAGE_MAP_SIZE = 45;
#endif /* RTMP_EFUSE_SUPPORT */
pChipCap->VcoPeriod = 10;
pChipCap->FlgIsVcoReCalMode = VCO_CAL_DISABLE;
pChipCap->WPDMABurstSIZE = 2; /* default 64B */
pChipCap->MBSSIDMode = MBSSID_MODE0;
RtmpChipBcnInit(pAd);
pChipOps->RxSensitivityTuning = RxSensitivityTuning;
#ifdef CONFIG_STA_SUPPORT
pChipOps->ChipAGCAdjust = ChipAGCAdjust;
#endif /* CONFIG_STA_SUPPORT */
pChipOps->ChipBBPAdjust = ChipBBPAdjust;
pChipOps->ChipSwitchChannel = Default_ChipSwitchChannel;
/* TX ALC */
pChipCap->bTempCompTxALC = FALSE;
pChipOps->AsicGetTxPowerOffset = NULL;
pChipOps->InitDesiredTSSITable = NULL;
pChipOps->AsicTxAlcGetAutoAgcOffset = NULL;
pChipOps->AsicExtraPowerOverMAC = NULL;
pChipOps->ChipAGCInit = Default_ChipAGCInit;
pChipOps->AsicAntennaDefaultReset = AsicAntennaDefaultReset;
pChipOps->NetDevNickNameInit = NetDevNickNameInit;
/* Init value. If pChipOps->AsicResetBbpAgent==NULL, "AsicResetBbpAgent" as default. If your chipset has specific routine, please re-hook it at self init function */
pChipOps->AsicResetBbpAgent = NULL;
pChipOps->InitTemperCompensation = NULL;
pChipOps->TemperCompensation = NULL;
#ifdef RT28xx
pChipOps->ChipSwitchChannel = RT28xx_ChipSwitchChannel;
#endif /* RT28xx */
#ifdef CARRIER_DETECTION_SUPPORT
pChipCap->carrier_func = DISABLE_TONE_RADAR;
pChipOps->ToneRadarProgram = NULL;
#endif /* CARRIER_DETECTOIN_SUPPORT */
#ifdef DFS_SUPPORT
pChipCap->DfsEngineNum = 4;
#endif /* DFS_SUPPORT */
pChipOps->CckMrcStatusCtrl = NULL;
pChipOps->RadarGLRTCompensate = NULL;
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#if defined(RT3883) || defined(RT3290) || defined(RT65xx) || defined(MT7601)
done:
#endif /* defined(RT3883) || defined(RT3290) || defined(RT65xx) || define(MT7601) */
DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipCap->bbpRegTbSize));
DBGPRINT(RT_DEBUG_TRACE, ("Chip VCO calibration mode = %d!\n", pChipCap->FlgIsVcoReCalMode));
}
/*
========================================================================
Routine Description: Read RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS rlt_rf_read(
IN RTMP_ADAPTER *pAd,
IN UCHAR bank,
IN UCHAR regID,
IN UCHAR *pValue)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i=0, k=0;
BOOLEAN rf_status;
NDIS_STATUS ret = STATUS_UNSUCCESSFUL;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxReadRFRegister. Not allow to read RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
rfcsr.word = 0;
for (i=0; i<MAX_BUSY_COUNT; i++)
{
if(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
goto done;
rf_status = rf_csr_poll_idle(pAd, &rfcsr.word);
if ( rf_status == BUSY)
break;
rfcsr.word = 0;
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
rfcsr.bank_65xx.RF_CSR_WR = 0;
rfcsr.bank_65xx.RF_CSR_KICK = 1;
rfcsr.bank_65xx.RF_CSR_REG_ID = regID;
rfcsr.bank_65xx.RF_CSR_REG_BANK = bank;
}
else
#endif /* RT65xx */
{
DBGPRINT_ERR(("RF[%d] read function for non-supported chip[0x%x]\n", regID, pAd->MACVersion));
break;
}
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
rf_status = rf_csr_poll_idle(pAd, &rfcsr.word);
if (rf_status == IDLE)
{
#ifdef RT65xx
if (IS_RT65XX(pAd) && (rfcsr.bank_65xx.RF_CSR_REG_ID == regID) &&
(rfcsr.bank_65xx.RF_CSR_REG_BANK == bank))
{
*pValue = (UCHAR)(rfcsr.bank_65xx.RF_CSR_DATA);
break;
}
#endif /* RT65xx */
}
}
if (rf_status == BUSY)
{
DBGPRINT_ERR(("RF read R%d=0x%X fail, i[%d], k[%d]\n", regID, rfcsr.word,i,k));
goto done;
}
ret = STATUS_SUCCESS;
done:
return ret;
}
