/** @brief: init state flag acc to info in huart * @details: used in Uart3Debug_Init, private ****************************************************************/ static HAL_StatusTypeDef MyHAL_UARTInit(UART_HandleTypeDef * huart) { /* Check the UART handle allocation */ if (huart == NULL) { return HAL_ERROR; } /* Check the parameters */ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); } else { assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->State == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; /* Init the low level hardware */ // HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); // HAL_NVIC_EnableIRQ(USART3_IRQn); } huart->State = HAL_UART_STATE_BUSY; /* Disable the peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ MyUARTSetConfig(huart); /* In asynchronous mode, the following bits must be kept cleared: * - LINEN and CLKEN bits in the USART_CR2 register, * - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); /* Enable the peripheral */ __HAL_UART_ENABLE(huart); /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->State = HAL_UART_STATE_READY; return HAL_OK; } /* MyHAL_UARTInit */
static int uart_stm32_configure(struct device *dev, const struct uart_config *cfg) { struct uart_stm32_data *data = DEV_DATA(dev); USART_TypeDef *UartInstance = UART_STRUCT(dev); const u32_t parity = uart_stm32_cfg2ll_parity(cfg->parity); const u32_t stopbits = uart_stm32_cfg2ll_stopbits(cfg->stop_bits); const u32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits); const u32_t flowctrl = uart_stm32_cfg2ll_hwctrl(cfg->flow_ctrl); /* Hardware doesn't support mark or space parity */ if ((UART_CFG_PARITY_MARK == cfg->parity) || (UART_CFG_PARITY_SPACE == cfg->parity)) { return -ENOTSUP; } #if defined(LL_USART_STOPBITS_0_5) && defined(CONFIG_LPUART_1) if (IS_LPUART_INSTANCE(UartInstance) && UART_CFG_STOP_BITS_0_5 == cfg->stop_bits) { return -ENOTSUP; } #else if (UART_CFG_STOP_BITS_0_5 == cfg->stop_bits) { return -ENOTSUP; } #endif #if defined(LL_USART_STOPBITS_1_5) && defined(CONFIG_LPUART_1) if (IS_LPUART_INSTANCE(UartInstance) && UART_CFG_STOP_BITS_1_5 == cfg->stop_bits) { return -ENOTSUP; } #else if (UART_CFG_STOP_BITS_1_5 == cfg->stop_bits) { return -ENOTSUP; } #endif /* Driver doesn't support 5 or 6 databits and potentially 7 or 9 */ if ((UART_CFG_DATA_BITS_5 == cfg->data_bits) || (UART_CFG_DATA_BITS_6 == cfg->data_bits) #ifndef LL_USART_DATAWIDTH_7B || (UART_CFG_DATA_BITS_7 == cfg->data_bits) #endif /* LL_USART_DATAWIDTH_7B */ #ifndef LL_USART_DATAWIDTH_9B || (UART_CFG_DATA_BITS_9 == cfg->data_bits) #endif /* LL_USART_DATAWIDTH_9B */ ) { return -ENOTSUP; } /* Driver supports only RTS CTS flow control */ if (UART_CFG_FLOW_CTRL_NONE != cfg->flow_ctrl) { if (!IS_UART_HWFLOW_INSTANCE(UartInstance) || UART_CFG_FLOW_CTRL_RTS_CTS != cfg->flow_ctrl) { return -ENOTSUP; } } LL_USART_Disable(UartInstance); if (parity != uart_stm32_get_parity(dev)) { uart_stm32_set_parity(dev, parity); } if (stopbits != uart_stm32_get_stopbits(dev)) { uart_stm32_set_stopbits(dev, stopbits); } if (databits != uart_stm32_get_databits(dev)) { uart_stm32_set_databits(dev, databits); } if (flowctrl != uart_stm32_get_hwctrl(dev)) { uart_stm32_set_hwctrl(dev, flowctrl); } if (cfg->baudrate != data->baud_rate) { uart_stm32_set_baudrate(dev, cfg->baudrate); data->baud_rate = cfg->baudrate; } LL_USART_Enable(UartInstance); return 0; };