/*
** configures arm interrupt controller to generate raster interrupt
*/
void SetupIntc(void)
{
#ifdef _TMS320C6X
IntDSPINTCInit();
IntRegister(C674X_MASK_INT4, LCDIsr);
IntEventMap(C674X_MASK_INT4, SYS_INT_LCDC_INT);
IntEnable(C674X_MASK_INT4);
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt.
*/
IntChannelSet(SYS_INT_LCDINT, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
IntSystemEnable(SYS_INT_I2CINT0);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/*
** Configures arm/dsp interrupt controller to generate frame interrupt
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
/* Initialize the DSP interrupt controller */
IntDSPINTCInit();
/* Register VPIF ISR to vector table */
IntRegister(C674X_MASK_INT5, VPIFIsr);
/* Map system interrupt to DSP maskable interrupt for VPIF */
IntEventMap(C674X_MASK_INT5, SYS_INT_VPIF_INT);
/* Enable DSP maskable interrupt for VPIF */
IntEnable(C674X_MASK_INT5);
/* Register LCD ISR to vector table */
IntRegister(C674X_MASK_INT6, LCDIsr);
/* Map system interrupt to DSP maskable interrupt for LCD */
IntEventMap(C674X_MASK_INT6, SYS_INT_LCDC_INT);
/* Enable DSP maskable interrupt for LCD */
IntEnable(C674X_MASK_INT6);
/* Enable DSP interrupts */
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_VPIF, VPIFIsr);
/* Set the channel number 2 of AINTC for LCD system interrupt. */
IntChannelSet(SYS_INT_VPIF, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_VPIF);
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt. */
IntChannelSet(SYS_INT_LCDINT, 3);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/*
** configures arm interrupt controller to generate PWM interrupts
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
// Initialize the DSP interrupt controller
IntDSPINTCInit();
// Register the ISRs to the vector table
IntRegister(C674X_MASK_INT4, PWMEventIsr);
IntRegister(C674X_MASK_INT5, PWMTZIsr);
// Map system events to the DSP maskable interrupts
IntEventMap(C674X_MASK_INT4, SYS_INT_EHRPWM1);
IntEventMap(C674X_MASK_INT5, SYS_INT_EHRPWM1TZ);
// Enable the DSP maskable interrupts
IntEnable(C674X_MASK_INT4);
IntEnable(C674X_MASK_INT5);
// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
IntSystemStatusClear(SYS_INT_EHRPWM1);
EHRPWMETIntClear(SOC_EHRPWM_1_REGS);
/************************PWM1****************************************/
IntRegister(SYS_INT_EHRPWM1, PWMEventIsr);
IntChannelSet(SYS_INT_EHRPWM1, 2);
IntSystemEnable(SYS_INT_EHRPWM1);
/********************************************************************/
IntRegister(SYS_INT_EHRPWM1TZ, PWMTZIsr);
IntChannelSet(SYS_INT_EHRPWM1TZ, 2);
IntSystemEnable(SYS_INT_EHRPWM1TZ);
/********************************************************************/
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
void
Interrupt_Init(void)
{
NVIC_EN1_R |= 0x00080000; // enable interrupt 51 in NVIC (GPIOJ)
NVIC_PRI12_R &= ~0xE0000000; // configure GPIOJ interrupt priority as 0
GPIO_PORTJ_AHB_IM_R |= 0x03; // arm interrupt on PJ0, PJ1
GPIO_PORTJ_AHB_IS_R &= ~0x03; // PJ0, PJ1 are edge-sensitive
GPIO_PORTJ_AHB_IBE_R &= ~0x03; // PJ0, PJ1 not both edges trigger
GPIO_PORTJ_AHB_IEV_R &= ~0x03; // PJ0, PJ1 falling edge event
IntGlobalEnable(); // globally enable interrupt
}
/*
** Set up the ARM Interrupt Controller for generating timer interrupt
*/
static void TimerIntrSetUp(void)
{
#ifdef _TMS320C6X
/* Initialize the DSPINTC */
IntDSPINTCInit();
/* Register the Timer ISR */
IntRegister(C674X_MASK_INT4, TimerIsr);
/* Map Timer interrupts to DSP maskable interrupt */
IntEventMap(C674X_MASK_INT4, SYS_INT_T64P2_TINTALL);
/* Enable DSP interrupt in DSPINTC */
IntEnable(C674X_MASK_INT4);
/* Enable DSP interrupts */
IntGlobalEnable();
#else
/* Initialize AINTC and register timer interrupt */
IntAINTCInit();
/* Register the Timer ISR */
IntRegister(SYS_INT_TIMR2_ALL, TimerIsr);
/* Set the channel number for Timer interrupt, it will map to IRQ */
IntChannelSet(SYS_INT_TIMR2_ALL, 2);
/* Enable IRQ for ARM (in CPSR)*/
IntMasterIRQEnable();
/* Enable AINTC interrupts in GER */
IntGlobalEnable();
/* Enable IRQ in AINTC */
IntIRQEnable();
/* Enable timer interrupts in AINTC */
IntSystemEnable(SYS_INT_TIMR2_ALL);
#endif
}
static void SetupInt(void)
{
#ifdef _TMS320C6X
// Initialize the DSP INTC
IntDSPINTCInit();
// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller(AINTC). */
IntAINTCInit();
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
static void SetupAINTCInt(void)
{
/*Initialize the ARM Interrupt Controller(AINTC). */
IntAINTCInit();
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
}
/**
* \brief Initialize the AINTC by enabling normal interrupts (IRQ) and fast interrupts (FIQ) on all required levels
*
* \return none
**/
void interrupt_init(void) {
/* Initialize AINTC - this should only be done once per application */
IntAINTCInit();
/* Enable IRQ for ARM (in CPSR)*/
IntMasterIRQEnable();
/* Enable AINTC interrupts in GER */
IntGlobalEnable();
/* Enable IRQ in AINTC */
IntIRQEnable();
IntMasterFIQEnable();
IntFIQEnable();
}
/*
** configures arm interrupt controller to generate raster interrupt
*/
static void SetupIntc(void)
{
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt.
*/
IntChannelSet(SYS_INT_LCDINT, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
}
static void EDMA3AINTCConfigure(void)
{
#if DEBUG_PRINT
UARTprintf("%s()\r\n", __FUNCTION__);
#endif
/* Initialize DSP interrupt controller */
IntDSPINTCInit();
IntRegister(C674X_MASK_INT4, Edma3CompletionIsr);
IntRegister(C674X_MASK_INT5, Edma3CCErrorIsr);
IntEventMap(C674X_MASK_INT4, SYS_INT_EDMA3_0_CC0_INT1);
IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_ERRINT);
IntEnable(C674X_MASK_INT4);
IntEnable(C674X_MASK_INT5);
IntRegister(C674X_MASK_INT6, MMCSDIsr);
IntEventMap(C674X_MASK_INT6, SYS_INT_MMCSD0_INT0);
IntEnable(C674X_MASK_INT6);
/* Enable DSP interrupts globally */
IntGlobalEnable();
}
static void SetupDSPINTCInt (void)
{
IntDSPINTCInit();
IntGlobalEnable();
}
/*
** The main function. Application starts here.
*/
int main(void)
{
unsigned short parToSend;
unsigned short parToLink;
/* Set up pin mux for I2C module 0 */
I2CPinMuxSetup(0);
McASPPinMuxSetup();
/* Power up the McASP module */
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_MCASP0, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
/* Power up EDMA3CC_0 and EDMA3TC_0 */
PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
#ifdef _TMS320C6X
// Initialize the DSP interrupt controller
IntDSPINTCInit();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
#endif
/* Initialize the I2C 0 interface for the codec AIC31 */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C, I2C_SLAVE_CODEC_AIC31);
EDMA3Init(SOC_EDMA30CC_0_REGS, 0);
EDMA3IntSetup();
McASPErrorIntSetup();
#ifdef _TMS320C6X
IntGlobalEnable();
#else
/* Enable the interrupts generation at global level */
IntMasterIRQEnable();
IntGlobalEnable();
IntIRQEnable();
#endif
/*
** Request EDMA channels. Channel 0 is used for reception and
** Channel 1 is used for transmission
*/
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_CHA_MCASP0_TX, EDMA3_CHA_MCASP0_TX, 0);
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_CHA_MCASP0_RX, EDMA3_CHA_MCASP0_RX, 0);
/* Initialize the DMA parameters */
I2SDMAParamInit();
/* Configure the Codec for I2S mode */
AIC31I2SConfigure();
/* Configure the McASP for I2S */
McASPI2SConfigure();
/* Activate the audio transmission and reception */
I2SDataTxRxActivate();
/*
** Looop forever. if a new buffer is received, the lastFullRxBuf will be
** updated in the rx completion ISR. if it is not the lastSentTxBuf,
** buffer is to be sent. This has to be mapped to proper paRAM set.
*/
while(1)
{
if(lastFullRxBuf != lastSentTxBuf)
{
/*
** Start the transmission from the link paramset. The param set
** 1 will be linked to param set at PAR_TX_START. So do not
** update paRAM set1.
*/
parToSend = PAR_TX_START + (parOffTxToSend % NUM_PAR);
parOffTxToSend = (parOffTxToSend + 1) % NUM_PAR;
parToLink = PAR_TX_START + parOffTxToSend;
lastSentTxBuf = (lastSentTxBuf + 1) % NUM_BUF;
ByteBuftoFloatBuf(rxBufPtr[lastFullRxBuf]);
/* Copy the buffer */
memcpy((void *)txBufPtr[lastSentTxBuf],
(void *)rxBufPtr[lastFullRxBuf],
AUDIO_BUF_SIZE);
/*
** Send the buffer by setting the DMA params accordingly.
** Here the buffer to send and number of samples are passed as
** parameters. This is important, if only transmit section
** is to be used.
*/
BufferTxDMAActivate(lastSentTxBuf, NUM_SAMPLES_PER_AUDIO_BUF,
(unsigned short)parToSend,
(unsigned short)parToLink);
}
}
}
