/*******************************************************************************
** Name: SpiDevDeInit
** Input:HDC dev
** Return: rk_err_t
** Owner:Aaron.sun
** Date: 2014.5.30
** Time: 9:18:00
*******************************************************************************/
_DRIVER_SPI_SPIDEVICE_INIT_
INIT FUN rk_err_t SpiDevDeInit(SPI_DEVICE_CLASS * pstSpiDev)
{
if(((DEVICE_CLASS*)pstSpiDev)->DevID == 0)
{
IntDisable(INT_ID_SPI0);
IntPendingClear(INT_ID_SPI0);
IntUnregister(INT_ID_SPI0);
ScuClockGateCtr(PCLK_SPI0_GATE,0);
}
else
{
IntDisable(INT_ID_SPI1);
IntPendingClear(INT_ID_SPI1);
IntUnregister(INT_ID_SPI1);
ScuClockGateCtr(PCLK_SPI1_GATE,0);
}
return RK_SUCCESS;
}
/*******************************************************************************
** Name: SpiDevInit
** Input:HDC dev
** Return: rk_err_t
** Owner:Aaron.sun
** Date: 2014.5.30
** Time: 9:18:00
*******************************************************************************/
_DRIVER_SPI_SPIDEVICE_INIT_
INIT FUN rk_err_t SpiDevInit(SPI_DEVICE_CLASS * pstSpiDev)
{
//open uart clk
if(((DEVICE_CLASS*)pstSpiDev)->DevID == 0)
{
ScuClockGateCtr(CLK_SPI0_GATE, 0);
ScuClockGateCtr(PCLK_SPI0_GATE, 0);
DelayMs(1);
ScuClockGateCtr(CLK_SPI0_GATE, 1);
ScuClockGateCtr(PCLK_SPI0_GATE, 1);
ScuSoftResetCtr(SPI0_SRST, 1);
DelayMs(1);
ScuSoftResetCtr(SPI0_SRST, 0);
//SetSPIFreq(0,PLL_MUX_CLK,96000000);
SetSPIFreq(0,XIN24M,24000000);
//open rst uart ip
}
else if(((DEVICE_CLASS*)pstSpiDev)->DevID == 1)
{
ScuClockGateCtr(CLK_SPI1_GATE, 1);
ScuClockGateCtr(PCLK_SPI1_GATE, 1);
SetSPIFreq(1,XIN24M,24000000);
//open rst uart ip
ScuSoftResetCtr(SPI1_SRST, 1);
DelayMs(1);
ScuSoftResetCtr(SPI1_SRST, 0);
}
SpiDevHwInit(((DEVICE_CLASS *)pstSpiDev)->DevID, pstSpiDev->CurCh);
SPIInit(((DEVICE_CLASS *)pstSpiDev)->DevID,0, pstSpiDev->stConfig[pstSpiDev->CurCh].SpiRate,
pstSpiDev->stConfig[pstSpiDev->CurCh].CtrlMode);
if(((DEVICE_CLASS *)pstSpiDev)->DevID == 0)
{
IntRegister(INT_ID_SPI0,SpiDevIntIsr0);
IntPendingClear(INT_ID_SPI0);
IntEnable(INT_ID_SPI0);
}
else if(((DEVICE_CLASS*)pstSpiDev)->DevID == 1)
{
IntRegister(INT_ID_SPI1,SpiDevIntIsr1);
IntPendingClear(INT_ID_SPI1);
IntEnable(INT_ID_SPI1);
}
return RK_SUCCESS;
}
/*******************************************************************************
** Name: SpiDevShellBspDMA_Write
** Input:HDC dev, uint8 * pstr
** Return: rk_err_t
** Owner:hj
** Date: 2014.12.9
** Time: 20:38:37
*******************************************************************************/
_DRIVER_SPI_SPIDEVICE_SHELL_
SHELL FUN rk_err_t SpiDevShellBspDMA_Write(HDC dev, uint8 * pstr)
{
rk_size_t realsize;
pSPI_REG Spi_Reg;
uint32 i = 0;
DEBUG("SpiDevShellBspDMA_Write %d\n",SPI_CH_TEST);
Spi_Reg = SpiGetCH(SPI_CH_TEST);
Spi_NeedTransLen = 0;
for(i=0;i<1024;i++)
{
Spi_TestBuffer[i++] = 0x55;
Spi_TestBuffer[i] = 0xaa;
}
//open uart clk
ScuClockGateCtr(HCLK_DMA_GATE, 1);
//open rst uart ip
ScuSoftResetCtr(SYSDMA_SRST, 1);
DelayMs(1);
ScuSoftResetCtr(SYSDMA_SRST, 0);
IntRegister(INT_ID_DMA ,SpiDMAIntIsr_Test);
IntPendingClear(INT_ID_DMA);
IntEnable(INT_ID_DMA);
DmaEnableInt(2);
SPIInit(SPI_CH_TEST,0, 12*1000*1000, SPI_CTL_TXRX_MASTER_TEST | TRANSMIT_ONLY);
SpiEanbleChannel(SPI_CH_TEST,0);
if(SPI_TRANSMIT_ONLY == SPI_TEST_MODE)
{
DEBUG("SPI_TRANSMIT_ONLY\n");
Spi_Testflag = 1;
SPIDmaWrite(SPI_CH_TEST);
if(SPI_CH0 == SPI_CH_TEST)
{
DmaConfig(2, (uint32)Spi_TestBuffer, (uint32)(&(Spi_Reg->SPI_TXDR)),1024, &SPI0ControlDmaCfg_TX, NULL);
}
else
{
DmaConfig(2, (uint32)Spi_TestBuffer, (uint32)(&(Spi_Reg->SPI_TXDR)),1024, &SPI1ControlDmaCfg_TX, NULL);
}
}
else
{
DEBUG("SPI_RECEIVE_ONLY\n");
//I2SInit(I2S_CH_TEST,I2S_SLAVE_MODE,I2S_EXT,I2S_TEST_FS,I2S_FORMAT,I2S_DATA_WIDTH16,I2S_NORMAL_MODE);
}
while(1);
}
/*******************************************************************************
** Name: SdcDevDeInit
** Input:HDC dev
** Return: rk_err_t
** Owner:Aaron.sun
** Date: 2014.2.19
** Time: 15:59:49
*******************************************************************************/
_DRIVER_SDMMC_SDMMCDEVICE_INIT_
rk_err_t SdcDevDeInit(SDC_DEVICE_CLASS * pstSdcDev)
{
if (pstSdcDev->enSdMmcPort == SDC0)
{
IntDisable(INT_ID_EMMC);
IntPendingClear(INT_ID_EMMC);
IntUnregister(INT_ID_EMMC);
}
else if (pstSdcDev->enSdMmcPort == SDC1)
{
IntDisable(INT_ID_SDMMC);
IntPendingClear(INT_ID_SDMMC);
IntUnregister(INT_ID_SDMMC);
}
//ScuClockGateCtr(CLOCK_GATE_SDMMC,0);
return RK_SUCCESS;
}
SHELL API rk_err_t hw_imdct_shell()
{
long *pSrc = test_data_imdct;
long *pDst ;
Hw_imdct_Init();
IntPendingClear(INT_ID_IMDCT);
IntRegister(INT_ID_IMDCT, imdct36_handler);
IntEnable(INT_ID_IMDCT);
imdct36_hw_pipeline(pSrc,pDst);
Hw_imdct_Exit();
{
int i;
int *imdct36_auto_output=&imdct36_auto_output_addr;
for (i = 0;i<36 ;i++)
{
if (imdct36_auto_output[i] != test_out_data_imdct[i])
{
break;
}
}
if (i == 36)
{
rk_print_string1("\r\n imdct test over");
return RK_SUCCESS;
}
else
{
rk_printf("\r\n imdct test error %d",i);
{
int i;
for(i = 0;i<36;i++)
{
rk_printf(" %0x,",imdct36_auto_output[i]);
if((i+1)%6 == 0)
{
rk_printf("\n");
}
}
}
return RK_ERROR ;
}
}
}
/**
* Interrupt Block
*/
void RegCtrlG2D::IntEnable(void)
{
IntPendingClear();
m_pG2DReg->INTEN = (0x1<<9);// + (0x1<<8) + (0x1); //Enable Interrupt
}
/*******************************************************************************
** Name: SpiDevShellBspDMA_ReadWrite
** Input:HDC dev, uint8 * pstr
** Return: rk_err_t
** Owner:hj
** Date: 2014.12.9
** Time: 20:39:07
*******************************************************************************/
_DRIVER_SPI_SPIDEVICE_SHELL_
SHELL FUN rk_err_t SpiDevShellBspDMA_ReadWrite(HDC dev, uint8 * pstr)
{
rk_size_t realsize,_RXrealsize;
pSPI_REG Spi_Reg0,Spi_Reg1;
uint8 Spi_clockBuffer[5] = {0,};
eSPI_ch_t spiChMaster,spiChSlave;
uint32 i = 0;
uint32 SPI0_RX_FIFO_ADDR, SPI0_TX_FIFO_ADDR,SPI1_RX_FIFO_ADDR,SPI1_TX_FIFO_ADDR;
Spi_Reg0 = SpiGetCH(SPI_CH0);
Spi_Reg1 = SpiGetCH(SPI_CH1);
SPI0_RX_FIFO_ADDR = SpiGetRxFIFOaddr(SPI_CH0);
SPI0_TX_FIFO_ADDR = SpiGetTxFIFOaddr(SPI_CH0);
SPI1_RX_FIFO_ADDR = SpiGetRxFIFOaddr(SPI_CH1);
SPI1_TX_FIFO_ADDR = SpiGetTxFIFOaddr(SPI_CH1);
if(StrCmpA(pstr, "0", 1) == 0)
{
spiChMaster = SPI_CH0;
spiChSlave = SPI_CH1;
DEBUG("Master-SPI0;Slave-SPI1\n");
}
else if(StrCmpA(pstr, "1", 1) == 0)
{
spiChMaster = SPI_CH1;
spiChSlave = SPI_CH0;
DEBUG("Master-SPI1;Slave-SPI0\n");
}
Spi_NeedTransLen = 0;
Spi_NeedTransLen_RX = 5;
Spi_Testflag = 1;
for(i=0;i<10;i++)
{
Spi_TestBuffer[i++] = 0x55;
Spi_TestBuffer[i] = 0xaa;
}
//open uart clk
ScuClockGateCtr(HCLK_DMA_GATE, 1);
//open rst uart ip
ScuSoftResetCtr(SYSDMA_SRST, 1);
DelayMs(1);
ScuSoftResetCtr(SYSDMA_SRST, 0);
IntRegister(INT_ID_DMA ,SpiDMAIntIsr_Test);
IntPendingClear(INT_ID_DMA);
IntEnable(INT_ID_DMA);
DmaEnableInt(2);
SPIInit(spiChMaster,0, 12*1000*1000, SPI_CTL_TXRX_MASTER_TEST);
SPIInit(spiChSlave,0, 12*1000*1000, SPI_CTL_TXRX_SLAVE_TEST);
SPIDmaRead(spiChSlave,5);
SpiEanbleChannel(spiChMaster,0);
SPIDmaWrite(spiChMaster);
//写入0x55 0xaa 0x55 0xaa 0x55 发送到slave
if(spiChMaster == SPI_CH0)
{
DmaConfig(2, (uint32)Spi_TestBuffer, (uint32)SPI0_TX_FIFO_ADDR,5, &SPI0ControlDmaCfg_TX, NULL);
}
else
{
DmaConfig(2, (uint32)Spi_TestBuffer, (uint32)SPI1_TX_FIFO_ADDR,5, &SPI1ControlDmaCfg_TX, NULL);
}
SpiGetInt(spiChMaster);
//SpiEnableTxInt(SPI_CH_TEST);
SpiWaitIdle(spiChMaster);
//从Slave读出0x55 0xaa 0x55 0xaa 0x55
DmaEnableInt(2);
if(spiChMaster == SPI_CH0)
{
DmaConfig(2, (uint32)SPI1_RX_FIFO_ADDR,(uint32)Spi_TestBuffer_Read, 5, &SPI1ControlDmaCfg_RX, NULL);
}
else
{
DmaConfig(2, (uint32)SPI0_RX_FIFO_ADDR,(uint32)Spi_TestBuffer_Read, 5, &SPI0ControlDmaCfg_RX, NULL);
}
//SPIReadFIFO(spiChSlave,Spi_TestBuffer_Read,5);
//读出master Read FIFO里面的无效数据
SPIReadFIFO(spiChMaster,&Spi_TestBuffer_Read[10],5);
//check
if((Spi_TestBuffer_Read[0] == 0x55)
&& (Spi_TestBuffer_Read[1] == 0xaa)
&& (Spi_TestBuffer_Read[2] == 0x55)
&& (Spi_TestBuffer_Read[3] == 0xaa)
&& (Spi_TestBuffer_Read[4] == 0x55))
{
//写入0x55 0xaa 0x55 0xaa 0x55 发送到master
//SPIDmaWrite(spiChSlave);
DmaEnableInt(2);
//写入数据，需要MASTER提供clock
if(spiChMaster == SPI_CH0)
{
DmaConfig(2, (uint32)Spi_TestBuffer, (uint32)SPI1_TX_FIFO_ADDR,5, &SPI1ControlDmaCfg_TX, NULL);
}
else
{
DmaConfig(2, (uint32)Spi_TestBuffer, (uint32)SPI0_TX_FIFO_ADDR,5, &SPI0ControlDmaCfg_TX, NULL);
}
//SPIWriteFIFO(spiChSlave,Spi_TestBuffer,5);
SPIWriteFIFO(spiChMaster,Spi_clockBuffer,5); //master 发送无效数据0x00，只提供clock
SpiGetInt(spiChMaster);
//SpiEnableTxInt(SPI_CH_TEST);
SpiWaitIdle(spiChMaster);
DelayMs(10);
//读出0x55 0xaa 0x55 0xaa 0x55
//SPIDmaRead(spiChMaster,5);
DmaEnableInt(2);
if(spiChMaster == SPI_CH0)
{
DmaConfig(2, (uint32)SPI0_RX_FIFO_ADDR,(uint32)&Spi_TestBuffer_Read[10], 5, &SPI0ControlDmaCfg_RX, NULL);
}
else
{
DmaConfig(2,(uint32)SPI1_RX_FIFO_ADDR,(uint32)&Spi_TestBuffer_Read[10],5, &SPI1ControlDmaCfg_RX, NULL);
}
//SPIReadFIFO(spiChMaster,&Spi_TestBuffer_Read[10],5);
if((Spi_TestBuffer_Read[10] == 0x55)
&& (Spi_TestBuffer_Read[11] == 0xaa)
&& (Spi_TestBuffer_Read[12] == 0x55)
&& (Spi_TestBuffer_Read[13] == 0xaa)
&& (Spi_TestBuffer_Read[14] == 0x55))
{
Spi_Testflag = 0;
}
}
while(Spi_Testflag);
DEBUG("SPI_TRANSMIT_RECEIVE is ok\n");
}
/*******************************************************************************
** Name: SpiDevShellBspPIO_Wtite
** Input:HDC dev, uint8 * pstr
** Return: rk_err_t
** Owner:hj
** Date: 2014.12.9
** Time: 20:37:26
*******************************************************************************/
_DRIVER_SPI_SPIDEVICE_SHELL_
SHELL FUN rk_err_t SpiDevShellBspPIO_Write(HDC dev, uint8 * pstr)
{
rk_size_t realsize;
uint32 i = 0;
DEBUG("SpiDevShellBspPIO_Write %d\n",SPI_CH_TEST);
Spi_NeedTransLen = 0;
for(i=0;i<1024;i++)
{
Spi_TestBuffer[i++] = 0x55;
Spi_TestBuffer[i] = 0xaa;
}
SPIInit(SPI_CH_TEST,0, 12*1000*1000, SPI_CTL_TXRX_MASTER_TEST | TRANSMIT_ONLY);
if(SPI_CH0 == SPI_CH_TEST)
{
IntRegister(INT_ID_SPI0 ,SpiIntIsr_Test_TX);
IntPendingClear(INT_ID_SPI0);
IntEnable(INT_ID_SPI0);
}
else
{
IntRegister(INT_ID_SPI1 ,SpiIntIsr_Test_TX);
IntPendingClear(INT_ID_SPI1);
IntEnable(INT_ID_SPI1);
}
if(SPI_TRANSMIT_ONLY == SPI_TEST_MODE)
{
SpiEanbleChannel(SPI_CH_TEST,0);
SPIPioWrite(SPI_CH_TEST);
DEBUG("SPI_TRANSMIT_ONLY\n");
while(1)
{
Spi_Testflag = 1;
realsize = SPIWriteFIFO(SPI_CH_TEST,Spi_TestBuffer,1024);
if(realsize == 1024)
{
SpiWaitIdle(SPI_CH_TEST);
}
else
{
Spi_NeedTransLen += realsize;
}
SpiGetInt(SPI_CH_TEST);
SpiEnableTxInt(SPI_CH_TEST);
SpiWaitIdle(SPI_CH_TEST);
while(Spi_Testflag);
}
}
else
{
DEBUG("SPI_RECEIVE_ONLY\n");
//I2SInit(I2S_CH_TEST,I2S_SLAVE_MODE,I2S_EXT,I2S_TEST_FS,I2S_FORMAT,I2S_DATA_WIDTH16,I2S_NORMAL_MODE);
}
while(1);
}
